This will allow us to fix the VGT_INDEX_TYPE issue properly.
Signed-off-by: Samuel Pitoiset <[email protected]>
---
src/amd/vulkan/radv_cmd_buffer.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index e508552781..b3f0ad0da7 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -979,6 +979,8 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer)
radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
cmd_buffer->state.emitted_pipeline = pipeline;
+
+ cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
}
static void
@@ -1398,6 +1400,8 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer)
radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) |
EVENT_INDEX(0));
}
+
+ cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
}
static void
@@ -1419,6 +1423,8 @@ radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
radeon_emit(cs, cmd_buffer->state.max_index_count);
+
+ cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
}
void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
@@ -1477,6 +1483,8 @@ radv_cmd_buffer_flush_dynamic_state(struct
radv_cmd_buffer *cmd_buffer)
if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS))
radv_emit_depth_biais(cmd_buffer);
+
+ cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_DYNAMIC_ALL;
}
static void
@@ -1787,8 +1795,6 @@ radv_cmd_buffer_flush_state(struct radv_cmd_buffer
*cmd_buffer,
assert(cmd_buffer->cs->cdw <= cdw_max);
si_emit_cache_flush(cmd_buffer);
-
- cmd_buffer->state.dirty = 0;
}
static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
--
2.14.2
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