On 01/17/2012 04:46 PM, Eric Anholt wrote:
On Tue, 17 Jan 2012 21:33:09 -0800, Kenneth Graunke<[email protected]>
wrote:
This is inspired by the BSpec, vol2a 3D Pipeline - Overview:
3D Pipeline / 3D Pipeline State Overview / Push Constant URB Allocation.
In particular, the last paragraph.
The new VS change fixes vertex scrambling in GLBenchmark PRO; the old VS
change is just for good measure/symmetry.
NOTE: This is a candidate for stable release branches.
Signed-off-by: Kenneth Graunke<[email protected]>
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 4 +++-
src/mesa/drivers/dri/i965/brw_vs_emit.c | 7 ++++++-
2 files changed, 9 insertions(+), 2 deletions(-)
I apologize for not having a specific quote from the spec. The text I cited
gave me the idea for the patch, but doesn't definitively say "yes, this is
required!".
vol2a 3D Pipeline, 3DSTATE_URB_VS says "512-bit URB rows", and our
gen7_urb.c math is urb_entry_size * 64 to get number of bytes, which
agrees with that usage for this field.
However, I don't see where aligning the size to an even number of
512-bit URB rows would be required. All I came up with is the write
length alignment on VS URB messages results in writing an extra 128-bit
row per entry, which isn't enough to matter.
You're right. Nack with extreme prejudice. I believe I've found the
actual problem; I'll send out the patch shortly.
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