---
src/amd/common/ac_nir_to_llvm.c | 16 ++++++++--------
src/amd/common/ac_shader_abi.h | 2 ++
src/gallium/drivers/radeonsi/si_shader.c | 14 ++++++--------
src/gallium/drivers/radeonsi/si_shader_internal.h | 2 --
4 files changed, 16 insertions(+), 18 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 483dd52b36..a82730f9f6 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -115,21 +115,20 @@ struct nir_to_llvm_context {
LLVMValueRef tes_rel_patch_id;
LLVMValueRef tes_patch_id;
LLVMValueRef tes_u;
LLVMValueRef tes_v;
LLVMValueRef gsvs_ring_stride;
LLVMValueRef gsvs_num_entries;
LLVMValueRef gs2vs_offset;
LLVMValueRef gs_wave_id;
LLVMValueRef gs_vtx_offset[6];
- LLVMValueRef gs_prim_id, gs_invocation_id;
LLVMValueRef esgs_ring;
LLVMValueRef gsvs_ring;
LLVMValueRef hs_ring_tess_offchip;
LLVMValueRef hs_ring_tess_factor;
LLVMValueRef prim_mask;
LLVMValueRef sample_pos_offset;
LLVMValueRef persp_sample, persp_center, persp_centroid;
LLVMValueRef linear_sample, linear_center, linear_centroid;
@@ -819,22 +818,22 @@ static void create_function(struct nir_to_llvm_context
*ctx,
add_user_sgpr_argument(&args, ctx->ac.i32,
&ctx->tcs_offchip_layout); // tcs offchip layout
else
radv_define_vs_user_sgprs_phase1(ctx, stage,
has_previous_stage, previous_stage, &args);
add_user_sgpr_argument(&args, ctx->ac.i32,
&ctx->gsvs_ring_stride); // gsvs stride
add_user_sgpr_argument(&args, ctx->ac.i32,
&ctx->gsvs_num_entries); // gsvs num entires
if (ctx->shader_info->info.needs_multiview_view_index)
add_user_sgpr_argument(&args, ctx->ac.i32,
&ctx->view_index);
add_vgpr_argument(&args, ctx->ac.i32,
&ctx->gs_vtx_offset[0]); // vtx01
add_vgpr_argument(&args, ctx->ac.i32,
&ctx->gs_vtx_offset[2]); // vtx23
- add_vgpr_argument(&args, ctx->ac.i32,
&ctx->gs_prim_id); // prim id
- add_vgpr_argument(&args, ctx->ac.i32,
&ctx->gs_invocation_id);
+ add_vgpr_argument(&args, ctx->ac.i32,
&ctx->abi.gs_prim_id); // prim id
+ add_vgpr_argument(&args, ctx->ac.i32,
&ctx->abi.gs_invocation_id);
add_vgpr_argument(&args, ctx->ac.i32,
&ctx->gs_vtx_offset[4]);
if (previous_stage == MESA_SHADER_VERTEX) {
add_vgpr_argument(&args, ctx->ac.i32,
&ctx->abi.vertex_id); // vertex id
add_vgpr_argument(&args, ctx->ac.i32,
&ctx->rel_auto_id); // rel auto id
add_vgpr_argument(&args, ctx->ac.i32,
&ctx->vs_prim_id); // vs prim id
add_vgpr_argument(&args, ctx->ac.i32,
&ctx->abi.instance_id); // instance id
} else {
add_vgpr_argument(&args, ctx->ac.f32,
&ctx->tes_u); // tes_u
add_vgpr_argument(&args, ctx->ac.f32,
&ctx->tes_v); // tes_v
@@ -845,26 +844,26 @@ static void create_function(struct nir_to_llvm_context
*ctx,
radv_define_common_user_sgprs_phase1(ctx, stage,
has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
radv_define_vs_user_sgprs_phase1(ctx, stage,
has_previous_stage, previous_stage, &args);
add_user_sgpr_argument(&args, ctx->ac.i32,
&ctx->gsvs_ring_stride); // gsvs stride
add_user_sgpr_argument(&args, ctx->ac.i32,
&ctx->gsvs_num_entries); // gsvs num entires
if (ctx->shader_info->info.needs_multiview_view_index)
add_user_sgpr_argument(&args, ctx->ac.i32,
&ctx->view_index);
add_sgpr_argument(&args, ctx->ac.i32,
&ctx->gs2vs_offset); // gs2vs offset
add_sgpr_argument(&args, ctx->ac.i32,
&ctx->gs_wave_id); // wave id
add_vgpr_argument(&args, ctx->ac.i32,
&ctx->gs_vtx_offset[0]); // vtx0
add_vgpr_argument(&args, ctx->ac.i32,
&ctx->gs_vtx_offset[1]); // vtx1
- add_vgpr_argument(&args, ctx->ac.i32,
&ctx->gs_prim_id); // prim id
+ add_vgpr_argument(&args, ctx->ac.i32,
&ctx->abi.gs_prim_id); // prim id
add_vgpr_argument(&args, ctx->ac.i32,
&ctx->gs_vtx_offset[2]);
add_vgpr_argument(&args, ctx->ac.i32,
&ctx->gs_vtx_offset[3]);
add_vgpr_argument(&args, ctx->ac.i32,
&ctx->gs_vtx_offset[4]);
add_vgpr_argument(&args, ctx->ac.i32,
&ctx->gs_vtx_offset[5]);
- add_vgpr_argument(&args, ctx->ac.i32,
&ctx->gs_invocation_id);
+ add_vgpr_argument(&args, ctx->ac.i32,
&ctx->abi.gs_invocation_id);
}
break;
case MESA_SHADER_FRAGMENT:
radv_define_common_user_sgprs_phase1(ctx, stage,
has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
if (ctx->shader_info->info.ps.needs_sample_positions)
add_user_sgpr_argument(&args, ctx->ac.i32,
&ctx->sample_pos_offset); /* sample position offset */
add_sgpr_argument(&args, ctx->ac.i32, &ctx->prim_mask); /* prim
mask */
add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_sample); /*
persp sample */
add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_center); /*
persp center */
add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_centroid);
/* persp centroid */
@@ -4008,26 +4007,27 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
case nir_intrinsic_load_draw_id:
result = ctx->abi->draw_id;
break;
case nir_intrinsic_load_view_index:
result = ctx->nctx->view_index ? ctx->nctx->view_index :
ctx->ac.i32_0;
break;
case nir_intrinsic_load_invocation_id:
if (ctx->stage == MESA_SHADER_TESS_CTRL)
result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids,
8, 5);
else
- result = ctx->nctx->gs_invocation_id;
+ result = ctx->abi->gs_invocation_id;
break;
case nir_intrinsic_load_primitive_id:
if (ctx->stage == MESA_SHADER_GEOMETRY) {
- ctx->nctx->shader_info->gs.uses_prim_id = true;
- result = ctx->nctx->gs_prim_id;
+ if (ctx->nctx)
+ ctx->nctx->shader_info->gs.uses_prim_id = true;
+ result = ctx->abi->gs_prim_id;
} else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
ctx->nctx->shader_info->tcs.uses_prim_id = true;
result = ctx->nctx->tcs_patch_id;
} else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
ctx->nctx->shader_info->tcs.uses_prim_id = true;
result = ctx->nctx->tes_patch_id;
} else
fprintf(stderr, "Unknown primitive id intrinsic: %d",
ctx->stage);
break;
case nir_intrinsic_load_sample_id:
diff --git a/src/amd/common/ac_shader_abi.h b/src/amd/common/ac_shader_abi.h
index 6ba1a51e07..20c26b8b02 100644
--- a/src/amd/common/ac_shader_abi.h
+++ b/src/amd/common/ac_shader_abi.h
@@ -37,20 +37,22 @@ enum ac_descriptor_type {
/* Document the shader ABI during compilation. This is what allows radeonsi and
* radv to share a compiler backend.
*/
struct ac_shader_abi {
LLVMValueRef base_vertex;
LLVMValueRef start_instance;
LLVMValueRef draw_id;
LLVMValueRef vertex_id;
LLVMValueRef instance_id;
+ LLVMValueRef gs_prim_id;
+ LLVMValueRef gs_invocation_id;
LLVMValueRef frag_pos[4];
LLVMValueRef front_face;
LLVMValueRef ancillary;
LLVMValueRef sample_coverage;
/* For VS and PS: pre-loaded shader inputs.
*
* Currently only used for NIR shaders; indexed by variables'
* driver_location.
*/
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index 746816d6a3..99c5ca4e27 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -761,22 +761,21 @@ static LLVMValueRef get_primitive_id(struct
si_shader_context *ctx,
case PIPE_SHADER_VERTEX:
return LLVMGetParam(ctx->main_fn,
ctx->param_vs_prim_id);
case PIPE_SHADER_TESS_CTRL:
return LLVMGetParam(ctx->main_fn,
ctx->param_tcs_patch_id);
case PIPE_SHADER_TESS_EVAL:
return LLVMGetParam(ctx->main_fn,
ctx->param_tes_patch_id);
case PIPE_SHADER_GEOMETRY:
- return LLVMGetParam(ctx->main_fn,
- ctx->param_gs_prim_id);
+ return ctx->abi.gs_prim_id;
default:
assert(0);
return ctx->i32_0;
}
}
/**
* Return the value of tgsi_ind_register for indexing.
* This is the indirect index with the constant offset added to it.
*/
@@ -1691,22 +1690,21 @@ void si_load_system_value(struct si_shader_context *ctx,
break;
case TGSI_SEMANTIC_DRAWID:
value = ctx->abi.draw_id;
break;
case TGSI_SEMANTIC_INVOCATIONID:
if (ctx->type == PIPE_SHADER_TESS_CTRL)
value = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
else if (ctx->type == PIPE_SHADER_GEOMETRY)
- value = LLVMGetParam(ctx->main_fn,
- ctx->param_gs_instance_id);
+ value = ctx->abi.gs_invocation_id;
else
assert(!"INVOCATIONID not implemented");
break;
case TGSI_SEMANTIC_POSITION:
{
LLVMValueRef pos[4] = {
LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
@@ -4612,22 +4610,22 @@ static void create_function(struct si_shader_context
*ctx)
add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR,
ctx->i32); /* unused */
}
declare_per_stage_desc_pointers(ctx, &fninfo,
ctx->type ==
PIPE_SHADER_GEOMETRY);
/* VGPRs (first GS, then VS/TES) */
ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR,
ctx->i32);
ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR,
ctx->i32);
- ctx->param_gs_prim_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
- ctx->param_gs_instance_id = add_arg(&fninfo, ARG_VGPR,
ctx->i32);
+ add_arg_assign(&fninfo, ARG_VGPR, ctx->i32,
&ctx->abi.gs_prim_id);
+ add_arg_assign(&fninfo, ARG_VGPR, ctx->i32,
&ctx->abi.gs_invocation_id);
ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR,
ctx->i32);
if (ctx->type == PIPE_SHADER_VERTEX) {
declare_vs_input_vgprs(ctx, &fninfo,
&num_prolog_vgprs);
} else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
declare_tes_input_vgprs(ctx, &fninfo);
}
if (ctx->type == PIPE_SHADER_VERTEX ||
@@ -4663,26 +4661,26 @@ static void create_function(struct si_shader_context
*ctx)
case PIPE_SHADER_GEOMETRY:
declare_global_desc_pointers(ctx, &fninfo);
declare_per_stage_desc_pointers(ctx, &fninfo, true);
ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
/* VGPRs */
add_arg_assign(&fninfo, ARG_VGPR, ctx->i32,
&ctx->gs_vtx_offset[0]);
add_arg_assign(&fninfo, ARG_VGPR, ctx->i32,
&ctx->gs_vtx_offset[1]);
- ctx->param_gs_prim_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
+ add_arg_assign(&fninfo, ARG_VGPR, ctx->i32,
&ctx->abi.gs_prim_id);
add_arg_assign(&fninfo, ARG_VGPR, ctx->i32,
&ctx->gs_vtx_offset[2]);
add_arg_assign(&fninfo, ARG_VGPR, ctx->i32,
&ctx->gs_vtx_offset[3]);
add_arg_assign(&fninfo, ARG_VGPR, ctx->i32,
&ctx->gs_vtx_offset[4]);
add_arg_assign(&fninfo, ARG_VGPR, ctx->i32,
&ctx->gs_vtx_offset[5]);
- ctx->param_gs_instance_id = add_arg(&fninfo, ARG_VGPR,
ctx->i32);
+ add_arg_assign(&fninfo, ARG_VGPR, ctx->i32,
&ctx->abi.gs_invocation_id);
break;
case PIPE_SHADER_FRAGMENT:
declare_global_desc_pointers(ctx, &fninfo);
declare_per_stage_desc_pointers(ctx, &fninfo, true);
add_arg_checked(&fninfo, ARG_SGPR, ctx->f32,
SI_PARAM_ALPHA_REF);
add_arg_checked(&fninfo, ARG_SGPR, ctx->i32,
SI_PARAM_PRIM_MASK);
add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32,
SI_PARAM_PERSP_SAMPLE);
add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32,
SI_PARAM_PERSP_CENTER);
diff --git a/src/gallium/drivers/radeonsi/si_shader_internal.h
b/src/gallium/drivers/radeonsi/si_shader_internal.h
index afb723d2ef..216f315c9a 100644
--- a/src/gallium/drivers/radeonsi/si_shader_internal.h
+++ b/src/gallium/drivers/radeonsi/si_shader_internal.h
@@ -176,22 +176,20 @@ struct si_shader_context {
int param_tes_u;
int param_tes_v;
int param_tes_rel_patch_id;
int param_tes_patch_id;
/* HW ES */
int param_es2gs_offset;
/* API GS */
int param_gs2vs_offset;
int param_gs_wave_id; /* GFX6 */
LLVMValueRef gs_vtx_offset[6]; /* in dwords (GFX6) */
- int param_gs_prim_id;
- int param_gs_instance_id;
int param_gs_vtx01_offset; /* in dwords (GFX9) */
int param_gs_vtx23_offset; /* in dwords (GFX9) */
int param_gs_vtx45_offset; /* in dwords (GFX9) */
/* CS */
int param_grid_size;
int param_block_size;
int param_block_id[3];
int param_thread_id;
LLVMTargetMachineRef tm;
--
2.14.3
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