nir_lower_io_to_temporaries() does not support tcs so we cannot
assume there are no indirects here. Also the radeonsi backend
(the only backend to support tess) has support for tcs indirects
so there is no need to lower them anyway.
---
src/mesa/state_tracker/st_glsl_to_nir.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index 90b65ee85ed..70c5daaa225 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -635,21 +635,22 @@ st_link_nir(struct gl_context *ctx,
* variant lowering.
*/
void
st_finalize_nir(struct st_context *st, struct gl_program *prog,
struct gl_shader_program *shader_program, nir_shader *nir)
{
struct pipe_screen *screen = st->pipe->screen;
NIR_PASS_V(nir, nir_split_var_copies);
NIR_PASS_V(nir, nir_lower_var_copies);
- NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects);
+ if (nir->info.stage != MESA_SHADER_TESS_CTRL)
+ NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects);
if (nir->info.stage == MESA_SHADER_VERTEX) {
/* Needs special handling so drvloc matches the vbo state: */
st_nir_assign_vs_in_locations(prog, nir);
/* Re-lower global vars, to deal with any dead VS inputs. */
NIR_PASS_V(nir, nir_lower_global_vars_to_local);
sort_varyings(&nir->outputs);
st_nir_assign_var_locations(&nir->outputs,
&nir->num_outputs,
--
2.14.3
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