Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
---
src/amd/common/ac_shader_util.c | 27 +++++++++++++++++++++
src/amd/common/ac_shader_util.h | 6 +++++
src/amd/vulkan/radv_pipeline.c | 32 +++++--------------------
src/gallium/drivers/radeonsi/si_state_shaders.c | 32 +++----------------------
4 files changed, 42 insertions(+), 55 deletions(-)
diff --git a/src/amd/common/ac_shader_util.c b/src/amd/common/ac_shader_util.c
index ab8d3ed49b..12f86dc677 100644
--- a/src/amd/common/ac_shader_util.c
+++ b/src/amd/common/ac_shader_util.c
@@ -78,3 +78,30 @@ ac_get_cb_shader_mask(unsigned spi_shader_col_format)
}
return cb_shader_mask;
}
+
+/**
+ * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
+ * geometry shader.
+ */
+uint32_t
+ac_vgt_gs_mode(unsigned gs_max_vert_out, enum chip_class chip_class)
+{
+ unsigned cut_mode;
+
+ if (gs_max_vert_out <= 128) {
+ cut_mode = V_028A40_GS_CUT_128;
+ } else if (gs_max_vert_out <= 256) {
+ cut_mode = V_028A40_GS_CUT_256;
+ } else if (gs_max_vert_out <= 512) {
+ cut_mode = V_028A40_GS_CUT_512;
+ } else {
+ assert(gs_max_vert_out <= 1024);
+ cut_mode = V_028A40_GS_CUT_1024;
+ }
+
+ return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
+ S_028A40_CUT_MODE(cut_mode)|
+ S_028A40_ES_WRITE_OPTIMIZE(chip_class <= VI) |
+ S_028A40_GS_WRITE_OPTIMIZE(1) |
+ S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0);
+}
diff --git a/src/amd/common/ac_shader_util.h b/src/amd/common/ac_shader_util.h
index d3804b8fb1..1bdf909e09 100644
--- a/src/amd/common/ac_shader_util.h
+++ b/src/amd/common/ac_shader_util.h
@@ -25,6 +25,9 @@
#define AC_SHADER_UTIL_H
#include <stdbool.h>
+#include <stdint.h>
+
+#include "amd_family.h"
unsigned
ac_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
@@ -33,4 +36,7 @@ ac_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
unsigned
ac_get_cb_shader_mask(unsigned spi_shader_col_format);
+uint32_t
+ac_vgt_gs_mode(unsigned gs_max_vert_out, enum chip_class chip_class);
+
#endif
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 1086f70d05..9daa2c9a1e 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1465,30 +1465,6 @@ static const struct radv_prim_vertex_count
prim_size_table[] = {
[V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
};
-static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs,
- enum chip_class chip_class)
-{
- unsigned gs_max_vert_out = gs->info.gs.vertices_out;
- unsigned cut_mode;
-
- if (gs_max_vert_out <= 128) {
- cut_mode = V_028A40_GS_CUT_128;
- } else if (gs_max_vert_out <= 256) {
- cut_mode = V_028A40_GS_CUT_256;
- } else if (gs_max_vert_out <= 512) {
- cut_mode = V_028A40_GS_CUT_512;
- } else {
- assert(gs_max_vert_out <= 1024);
- cut_mode = V_028A40_GS_CUT_1024;
- }
-
- return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
- S_028A40_CUT_MODE(cut_mode)|
- S_028A40_ES_WRITE_OPTIMIZE(chip_class <= VI) |
- S_028A40_GS_WRITE_OPTIMIZE(1) |
- S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0);
-}
-
static struct ac_vs_output_info *get_vs_output_info(struct radv_pipeline
*pipeline)
{
if (radv_pipeline_has_gs(pipeline))
@@ -1507,8 +1483,12 @@ static void calculate_vgt_gs_mode(struct radv_pipeline
*pipeline)
pipeline->graphics.vgt_gs_mode = 0;
if (radv_pipeline_has_gs(pipeline)) {
- pipeline->graphics.vgt_gs_mode =
si_vgt_gs_mode(pipeline->shaders[MESA_SHADER_GEOMETRY],
-
pipeline->device->physical_device->rad_info.chip_class);
+ struct radv_shader_variant *gs =
+ pipeline->shaders[MESA_SHADER_GEOMETRY];
+
+ pipeline->graphics.vgt_gs_mode =
+ ac_vgt_gs_mode(gs->info.gs.vertices_out,
+
pipeline->device->physical_device->rad_info.chip_class);
} else if (outinfo->export_prim_id) {
pipeline->graphics.vgt_gs_mode =
S_028A40_MODE(V_028A40_GS_SCENARIO_A);
pipeline->graphics.vgt_primitiveid_en = true;
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index d33008cdda..9143f61fcd 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -573,34 +573,6 @@ static void si_shader_es(struct si_screen *sscreen, struct
si_shader *shader)
polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
}
-/**
- * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
- * geometry shader.
- */
-static uint32_t si_vgt_gs_mode(struct si_shader_selector *sel)
-{
- enum chip_class chip_class = sel->screen->info.chip_class;
- unsigned gs_max_vert_out = sel->gs_max_out_vertices;
- unsigned cut_mode;
-
- if (gs_max_vert_out <= 128) {
- cut_mode = V_028A40_GS_CUT_128;
- } else if (gs_max_vert_out <= 256) {
- cut_mode = V_028A40_GS_CUT_256;
- } else if (gs_max_vert_out <= 512) {
- cut_mode = V_028A40_GS_CUT_512;
- } else {
- assert(gs_max_vert_out <= 1024);
- cut_mode = V_028A40_GS_CUT_1024;
- }
-
- return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
- S_028A40_CUT_MODE(cut_mode)|
- S_028A40_ES_WRITE_OPTIMIZE(chip_class <= VI) |
- S_028A40_GS_WRITE_OPTIMIZE(1) |
- S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0);
-}
-
struct gfx9_gs_info {
unsigned es_verts_per_subgroup;
unsigned gs_prims_per_subgroup;
@@ -867,7 +839,9 @@ static void si_shader_vs(struct si_screen *sscreen, struct
si_shader *shader,
si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, S_028A40_MODE(mode));
si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN,
enable_prim_id);
} else {
- si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
+ si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
+ ac_vgt_gs_mode(gs->gs_max_out_vertices,
+ sscreen->info.chip_class));
si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
}
--
2.15.1
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
