From: Dave Airlie <[email protected]> amdvlk is probably more subtle than this but it never uses the inv cb/db variants, we fail some CTS tests without this.
Fixes: dEQP-VK.renderpass.dedicated_allocation.formats.d32_sfloat_s8_uint.input*. Fixes: c2fbeb7ca05 (radv: add GFX9 cache flushing support.) Signed-off-by: Dave Airlie <[email protected]> --- src/amd/vulkan/si_cmd_buffer.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 972d37948a..a6981c136e 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -991,6 +991,11 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs, if (chip_class >= GFX9 && flush_cb_db) { unsigned cb_db_event, tc_flags; +#if 0 + /* This breaks a bunch of: + dEQP-VK.renderpass.dedicated_allocation.formats.d32_sfloat_s8_uint.input*. + use the big hammer always. + */ /* Set the CB/DB flush event. */ switch (flush_cb_db) { case RADV_CMD_FLAG_FLUSH_AND_INV_CB: @@ -1003,7 +1008,9 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs, /* both CB & DB */ cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT; } - +#else + cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT; +#endif /* TC | TC_WB = invalidate L2 data * TC_MD | TC_WB = invalidate L2 metadata * TC | TC_WB | TC_MD = invalidate L2 data & metadata -- 2.14.3 _______________________________________________ mesa-dev mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-dev
