If we import an image, we might not have space in the
buffer for CMASK, even though it is compatible.
---
src/amd/vulkan/radv_image.c | 43 ++++++++++++++++++++++++-------------------
src/amd/vulkan/radv_private.h | 1 +
2 files changed, 25 insertions(+), 19 deletions(-)
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 316ce2e2ba..d69ae8af48 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -923,29 +923,34 @@ radv_image_create(VkDevice _device,
image->size = image->surface.surf_size;
image->alignment = image->surface.surf_alignment;
- /* Try to enable DCC first. */
- if (radv_image_can_enable_dcc(image)) {
- radv_image_alloc_dcc(image);
- } else {
- /* When DCC cannot be enabled, try CMASK. */
- image->surface.dcc_size = 0;
- if (radv_image_can_enable_cmask(image)) {
- radv_image_alloc_cmask(device, image);
+ if (!create_info->no_metadata_planes) {
+ /* Try to enable DCC first. */
+ if (radv_image_can_enable_dcc(image)) {
+ radv_image_alloc_dcc(image);
+ } else {
+ /* When DCC cannot be enabled, try CMASK. */
+ image->surface.dcc_size = 0;
+ if (radv_image_can_enable_cmask(image)) {
+ radv_image_alloc_cmask(device, image);
+ }
}
- }
- /* Try to enable FMASK for multisampled images. */
- if (radv_image_can_enable_fmask(image)) {
- radv_image_alloc_fmask(device, image);
- } else {
- /* Otherwise, try to enable HTILE for depth surfaces. */
- if (radv_image_can_enable_htile(image) &&
- !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
- radv_image_alloc_htile(image);
- image->tc_compatible_htile = image->surface.flags &
RADEON_SURF_TC_COMPATIBLE_HTILE;
+ /* Try to enable FMASK for multisampled images. */
+ if (radv_image_can_enable_fmask(image)) {
+ radv_image_alloc_fmask(device, image);
} else {
- image->surface.htile_size = 0;
+ /* Otherwise, try to enable HTILE for depth surfaces. */
+ if (radv_image_can_enable_htile(image) &&
+ !(device->instance->debug_flags &
RADV_DEBUG_NO_HIZ)) {
+ radv_image_alloc_htile(image);
+ image->tc_compatible_htile =
image->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
+ } else {
+ image->surface.htile_size = 0;
+ }
}
+ } else {
+ image->surface.dcc_size = 0;
+ image->surface.htile_size = 0;
}
if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index bae353c0e5..c15b044d00 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1426,6 +1426,7 @@ struct radv_image_view {
struct radv_image_create_info {
const VkImageCreateInfo *vk_info;
bool scanout;
+ bool no_metadata_planes;
};
VkResult radv_image_create(VkDevice _device,
--
2.16.0.rc0.223.g4a4ac83678-goog
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