From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeonsi/si_pm4.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_pm4.c
b/src/gallium/drivers/radeonsi/si_pm4.c
index 96e4e1d..06b3fe8 100644
--- a/src/gallium/drivers/radeonsi/si_pm4.c
+++ b/src/gallium/drivers/radeonsi/si_pm4.c
@@ -160,22 +160,22 @@ void si_pm4_upload_indirect_buffer(struct si_context
*sctx,
/* only supported on CIK and later */
if (sctx->b.chip_class < CIK)
return;
assert(state->ndw);
assert(aligned_ndw <= SI_PM4_MAX_DW);
r600_resource_reference(&state->indirect_buffer, NULL);
state->indirect_buffer = (struct r600_resource*)
- pipe_buffer_create(screen, 0,
- PIPE_USAGE_DEFAULT, aligned_ndw * 4);
+ si_aligned_buffer_create(screen, R600_RESOURCE_FLAG_READ_ONLY,
+ PIPE_USAGE_DEFAULT, aligned_ndw * 4,
256);
if (!state->indirect_buffer)
return;
/* Pad the IB to 8 DWs to meet CP fetch alignment requirements. */
if (sctx->screen->info.gfx_ib_pad_with_type2) {
for (int i = state->ndw; i < aligned_ndw; i++)
state->pm4[i] = 0x80000000; /* type2 nop packet */
} else {
for (int i = state->ndw; i < aligned_ndw; i++)
state->pm4[i] = 0xffff1000; /* type3 nop packet */
--
2.7.4
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