---
src/intel/compiler/brw_nir.h | 2 ++
src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp | 29 ++++++++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/src/intel/compiler/brw_nir.h b/src/intel/compiler/brw_nir.h
index 809d4c338d..a29d858806 100644
--- a/src/intel/compiler/brw_nir.h
+++ b/src/intel/compiler/brw_nir.h
@@ -145,6 +145,8 @@ void brw_nir_setup_arb_uniforms(void *mem_ctx, nir_shader
*shader,
struct gl_program *prog,
struct brw_stage_prog_data *stage_prog_data);
+void brw_nir_lower_tcs_vertices_in_to_uniform(nir_shader *nir);
+
void brw_nir_analyze_ubo_ranges(const struct brw_compiler *compiler,
nir_shader *nir,
struct brw_ubo_range out_ranges[4]);
diff --git a/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp
b/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp
index 9e135cbb1a..38498833a7 100644
--- a/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp
+++ b/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp
@@ -243,3 +243,32 @@ brw_nir_setup_arb_uniforms(void *mem_ctx, nir_shader
*shader,
stage_prog_data->param[4 * p + i] = BRW_PARAM_BUILTIN_ZERO;
}
}
+
+void
+brw_nir_lower_tcs_vertices_in_to_uniform(nir_shader *nir)
+{
+ assert(nir->info.stage == MESA_SHADER_TESS_CTRL);
+
+ int uniform = -1;
+ nir_foreach_variable_safe(var, &nir->system_values) {
+ if (var->data.location != SYSTEM_VALUE_VERTICES_IN)
+ continue;
+
+ if (uniform == -1) {
+ gl_state_index tokens[STATE_LENGTH] = {
+ STATE_INTERNAL,
+ STATE_TCS_PATCH_VERTICES_IN,
+ };
+ var->num_state_slots = 1;
+ var->state_slots =
+ ralloc_array(var, nir_state_slot, var->num_state_slots);
+ memcpy(var->state_slots[0].tokens, tokens, sizeof(tokens));
+ var->state_slots[0].swizzle = SWIZZLE_XXXX;
+ }
+
+ var->data.mode = nir_var_uniform;
+ var->data.location = uniform;
+ exec_node_remove(&var->node);
+ exec_list_push_tail(&nir->uniforms, &var->node);
+ }
+}
--
2.11.0
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