Am Mittwoch, den 10.01.2018, 15:27 -0500 schrieb Ilia Mirkin: [...] > > If your hardware executes all the vertices in parallel, then a > barrier should be unnecessary.
My first try for this patch did not include forcing the barrier into slot x, which in turn resulted in failing piglits, e.g. tcs-output-array-float-index-rd-after-barrier and I'm quite confident that the LDS r/w order was not broken - also because just forcing the barrier into slot x fixed it, so I guess not all vertices are always processed in parallel, which is also no surprise since the number of shader units attributed to the TCS stage is limited. Best, Gert _______________________________________________ mesa-dev mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-dev
