---
src/amd/vulkan/radv_cmd_buffer.c | 37 +++++++++++++++++++++++--------------
src/amd/vulkan/radv_meta_buffer.c | 5 +++--
src/amd/vulkan/radv_private.h | 6 ++++--
src/amd/vulkan/si_cmd_buffer.c | 5 +++--
4 files changed, 33 insertions(+), 20 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 67799a13cc..6dfae4d5e3 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -297,10 +297,11 @@ radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
void *fence_ptr;
+ struct radeon_winsys_bo *upload_bo;
radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
- &cmd_buffer->gfx9_fence_offset,
+ &upload_bo,
&cmd_buffer->gfx9_fence_offset,
&fence_ptr);
- cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
+ cmd_buffer->gfx9_fence_bo = upload_bo;
}
cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
@@ -362,6 +363,7 @@ bool
radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
unsigned size,
unsigned alignment,
+ struct radeon_winsys_bo **bo,
unsigned *out_offset,
void **ptr)
{
@@ -374,6 +376,7 @@ radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer,
*out_offset = offset;
*ptr = cmd_buffer->upload.map + offset;
+ *bo = cmd_buffer->upload.upload_bo;
cmd_buffer->upload.offset = offset + size;
return true;
@@ -382,12 +385,13 @@ radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer,
bool
radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
unsigned size, unsigned alignment,
- const void *data, unsigned *out_offset)
+ const void *data, struct radeon_winsys_bo **bo,
+ unsigned *out_offset)
{
uint8_t *ptr;
if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
- out_offset, (void **)&ptr))
+ bo, out_offset, (void **)&ptr))
return false;
if (ptr)
@@ -1709,13 +1713,14 @@ radv_flush_push_descriptors(struct radv_cmd_buffer
*cmd_buffer)
{
struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
unsigned bo_offset;
+ struct radeon_winsys_bo *bo;
if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
set->mapped_ptr,
- &bo_offset))
+ &bo, &bo_offset))
return;
- set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
+ set->va = radv_buffer_get_va(bo);
set->va += bo_offset;
}
@@ -1725,9 +1730,10 @@ radv_flush_indirect_descriptor_sets(struct
radv_cmd_buffer *cmd_buffer)
uint32_t size = MAX_SETS * 2 * 4;
uint32_t offset;
void *ptr;
+ struct radeon_winsys_bo *bo;
if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
- 256, &offset, &ptr))
+ 256, &bo, &offset, &ptr))
return;
for (unsigned i = 0; i < MAX_SETS; i++) {
@@ -1740,7 +1746,7 @@ radv_flush_indirect_descriptor_sets(struct
radv_cmd_buffer *cmd_buffer)
uptr[1] = set_va >> 32;
}
- uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
+ uint64_t va = radv_buffer_get_va(bo);
va += offset;
if (cmd_buffer->state.pipeline) {
@@ -1822,16 +1828,17 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
(!layout->push_constant_size && !layout->dynamic_offset_count))
return;
+ struct radeon_winsys_bo *upload_bo;
if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
layout->push_constant_size +
16 * layout->dynamic_offset_count,
- 256, &offset, &ptr))
+ 256, &upload_bo, &offset, &ptr))
return;
memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
memcpy((char*)ptr + layout->push_constant_size,
cmd_buffer->dynamic_buffers,
16 * layout->dynamic_offset_count);
- va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
+ va = radv_buffer_get_va(upload_bo);
va += offset;
MAYBE_UNUSED unsigned cdw_max =
radeon_check_space(cmd_buffer->device->ws,
@@ -1861,10 +1868,11 @@ radv_cmd_buffer_update_vertex_descriptors(struct
radv_cmd_buffer *cmd_buffer, bo
uint32_t i = 0;
uint32_t count = velems->count;
uint64_t va;
+ struct radeon_winsys_bo *upload_bo;
/* allocate some descriptor state for vertex buffers */
if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
- &vb_offset, &vb_ptr))
+ &upload_bo, &vb_offset,
&vb_ptr))
return false;
for (i = 0; i < count; i++) {
@@ -1887,7 +1895,7 @@ radv_cmd_buffer_update_vertex_descriptors(struct
radv_cmd_buffer *cmd_buffer, bo
desc[3] = velems->rsrc_word3[i];
}
- va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
+ va = radv_buffer_get_va(upload_bo);
va += vb_offset;
radv_emit_userdata_address(cmd_buffer,
cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
@@ -2522,6 +2530,7 @@ void radv_meta_push_descriptor_set(
RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
struct radv_descriptor_set *push_set =
&cmd_buffer->meta_push_descriptors;
unsigned bo_offset;
+ struct radeon_winsys_bo *upload_bo;
assert(set == 0);
assert(layout->set[set].layout->flags &
VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
@@ -2530,11 +2539,11 @@ void radv_meta_push_descriptor_set(
push_set->layout = layout->set[set].layout;
if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
- &bo_offset,
+ &upload_bo, &bo_offset,
(void**) &push_set->mapped_ptr))
return;
- push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
+ push_set->va = radv_buffer_get_va(upload_bo);
push_set->va += bo_offset;
radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
diff --git a/src/amd/vulkan/radv_meta_buffer.c
b/src/amd/vulkan/radv_meta_buffer.c
index e6ad235e93..64178bf2e2 100644
--- a/src/amd/vulkan/radv_meta_buffer.c
+++ b/src/amd/vulkan/radv_meta_buffer.c
@@ -529,8 +529,9 @@ void radv_CmdUpdateBuffer(
radv_cmd_buffer_trace_emit(cmd_buffer);
} else {
uint32_t buf_offset;
- radv_cmd_buffer_upload_data(cmd_buffer, dataSize, 32, pData,
&buf_offset);
- radv_copy_buffer(cmd_buffer, cmd_buffer->upload.upload_bo,
dst_buffer->bo,
+ struct radeon_winsys_bo *src_bo;
+ radv_cmd_buffer_upload_data(cmd_buffer, dataSize, 32, pData,
&src_bo, &buf_offset);
+ radv_copy_buffer(cmd_buffer, src_bo, dst_buffer->bo,
buf_offset, dstOffset + dst_buffer->offset,
dataSize);
}
}
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index c39358951d..f0f31d0698 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1033,6 +1033,7 @@ bool
radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
unsigned size,
unsigned alignment,
+ struct radeon_winsys_bo **bo,
unsigned *out_offset,
void **ptr);
void
@@ -1041,8 +1042,9 @@ radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer,
bool transitions);
bool
radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
- unsigned size, unsigned alignmnet,
- const void *data, unsigned *out_offset);
+ unsigned size, unsigned alignment,
+ const void *data, struct radeon_winsys_bo **bo,
+ unsigned *out_offset);
void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index f5f4eefcd2..5bf9851803 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -1300,12 +1300,13 @@ static void si_cp_dma_realign_engine(struct
radv_cmd_buffer *cmd_buffer, unsigne
unsigned dma_flags = 0;
unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
void *ptr;
+ struct radeon_winsys_bo *bo;
assert(size < SI_CPDMA_ALIGNMENT);
- radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT,
&offset, &ptr);
+ radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT,
&bo, &offset, &ptr);
- va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
+ va = radv_buffer_get_va(bo);
va += offset;
si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
--
2.15.1
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