Hi Mark,

thanks for point them out. [PATCH v3 3/8] / [PATCH v3 4/8] / [PATCH v3 5/8] update according.

James.


On 2018-02-08 05:23 PM, Mark Thompson wrote:
On 06/02/18 20:05, James Zhu wrote:
Implement UVD hevc encode functions

Signed-off-by: James Zhu <james....@amd.com>
---
  src/gallium/drivers/radeon/radeon_uvd_enc.c | 370 ++++++++++++++++++++++++++++
  1 file changed, 370 insertions(+)
  create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.c

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc.c
new file mode 100644
index 0000000..f162589
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.c
@@ -0,0 +1,370 @@
+/**************************************************************************
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **************************************************************************/
+
+#include <stdio.h>
+
+#include "pipe/p_video_codec.h"
+
+#include "util/u_video.h"
+#include "util/u_memory.h"
+
+#include "vl/vl_video_buffer.h"
+
+#include "radeonsi/si_pipe.h"
+#include "radeon_video.h"
+#include "radeon_uvd_enc.h"
+
+static void
+radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc,
+                         struct pipe_h265_enc_picture_desc *pic)
+{
+   enc->enc_pic.picture_type = pic->picture_type;
+   enc->enc_pic.frame_num = pic->frame_num;
+   enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
+   enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
+   enc->enc_pic.ref_idx_l0 = pic->ref_idx_l0;
+   enc->enc_pic.ref_idx_l1 = pic->ref_idx_l1;
+   enc->enc_pic.not_referenced = pic->not_referenced;
+   enc->enc_pic.is_idr = (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_IDR)
+      || (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_I);
Looks very suspicious?  I would expect that only IDR frames would be IDR.

+   enc->enc_pic.crop_left = 0;
+   enc->enc_pic.crop_right =
+      (align(enc->base.width, 16) - enc->base.width) / 2;
+   enc->enc_pic.crop_top = 0;
+   enc->enc_pic.crop_bottom =
+      (align(enc->base.height, 16) - enc->base.height) / 2;
+   enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
+   enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
+   enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
+   enc->enc_pic.max_poc = pic->seq.intra_period;
+   enc->enc_pic.log2_max_poc = 0;
+   for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
+      i = (i >> 1);
+   enc->enc_pic.chroma_format_idc = pic->seq.chroma_format_idc;
+   enc->enc_pic.pic_width_in_luma_samples =
+      pic->seq.pic_width_in_luma_samples;
+   enc->enc_pic.pic_height_in_luma_samples =
+      pic->seq.pic_height_in_luma_samples;
+   enc->enc_pic.log2_diff_max_min_luma_coding_block_size =
+      pic->seq.log2_diff_max_min_luma_coding_block_size;
+   enc->enc_pic.log2_min_transform_block_size_minus2 =
+      pic->seq.log2_min_transform_block_size_minus2;
+   enc->enc_pic.log2_diff_max_min_transform_block_size =
+      pic->seq.log2_diff_max_min_transform_block_size;
+   enc->enc_pic.max_transform_hierarchy_depth_inter =
+      pic->seq.max_transform_hierarchy_depth_inter;
+   enc->enc_pic.max_transform_hierarchy_depth_intra =
+      pic->seq.max_transform_hierarchy_depth_intra;
+   enc->enc_pic.log2_parallel_merge_level_minus2 =
+      pic->pic.log2_parallel_merge_level_minus2;
+   enc->enc_pic.bit_depth_luma_minus8 = pic->seq.bit_depth_luma_minus8;
+   enc->enc_pic.bit_depth_chroma_minus8 = pic->seq.bit_depth_chroma_minus8;
+   enc->enc_pic.nal_unit_type = pic->pic.nal_unit_type;
+   enc->enc_pic.max_num_merge_cand = pic->slice.max_num_merge_cand;
+   enc->enc_pic.sample_adaptive_offset_enabled_flag =
+      pic->seq.sample_adaptive_offset_enabled_flag;
+   enc->enc_pic.pcm_enabled_flag = pic->seq.pcm_enabled_flag;
+   enc->enc_pic.sps_temporal_mvp_enabled_flag =
+      pic->seq.sps_temporal_mvp_enabled_flag;
+}
+
+static void
+flush(struct radeon_uvd_encoder *enc)
+{
+   enc->ws->cs_flush(enc->cs, PIPE_FLUSH_ASYNC, NULL);
+}
+
+static void
+radeon_uvd_enc_flush(struct pipe_video_codec *encoder)
+{
+   struct radeon_uvd_encoder *enc = (struct radeon_uvd_encoder *) encoder;
+   flush(enc);
+}
+
+static void
+radeon_uvd_enc_cs_flush(void *ctx, unsigned flags,
+                        struct pipe_fence_handle **fence)
+{
+   // just ignored
+}
+
+static unsigned
+get_cpb_num(struct radeon_uvd_encoder *enc)
+{
+   unsigned w = align(enc->base.width, 16) / 16;
+   unsigned h = align(enc->base.height, 16) / 16;
+   unsigned dpb;
+
+   switch (enc->base.level) {
+   case 10:
+      dpb = 396;
+      break;
+   case 11:
+      dpb = 900;
+      break;
+   case 12:
+   case 13:
+   case 20:
+      dpb = 2376;
+      break;
+   case 21:
+      dpb = 4752;
+      break;
+   case 22:
+   case 30:
+      dpb = 8100;
+      break;
+   case 31:
+      dpb = 18000;
+      break;
+   case 32:
+      dpb = 20480;
+      break;
+   case 40:
+   case 41:
+      dpb = 32768;
+      break;
+   case 42:
+      dpb = 34816;
+      break;
+   case 50:
+      dpb = 110400;
+      break;
+   default:
+   case 51:
+   case 52:
+      dpb = 184320;
+      break;
This appears to be copied from H.264 - the H.265 values are not the same.

Also, there are levels 6, 6.1 and 6.2.

+   }
+
+   return MIN2(dpb / (w * h), 16);
+}
+
...

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