All this information can be retrieved from the TIC directly. Avoid having to dip into the constbuf information about the image.
Signed-off-by: Ilia Mirkin <[email protected]> --- .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 61 +++++++++++++++++++++- .../nouveau/codegen/nv50_ir_lowering_nvc0.h | 1 + 2 files changed, 61 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp index e07f57e782d..ddcae1e5a51 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp @@ -1784,6 +1784,62 @@ static inline uint16_t getSuClampSubOp(const TexInstruction *su, int c) } bool +NVC0LoweringPass::handleSUQGM107(TexInstruction *suq) +{ + Value *ind = suq->getIndirectR(); + Value *handle; + const int slot = suq->tex.r; + const int mask = suq->tex.mask; + + if (suq->tex.bindless) + handle = ind; + else + handle = loadTexHandle(ind, slot + 32); + + suq->tex.r = 0xff; + suq->tex.s = 0x1f; + + suq->setIndirectR(NULL); + suq->setSrc(0, handle); + suq->tex.rIndirectSrc = 0; + suq->setSrc(1, bld.loadImm(NULL, 0)); + suq->tex.query = TXQ_DIMS; + suq->op = OP_TXQ; + + // We store CUBE / CUBE_ARRAY as a 2D ARRAY. Make sure that depth gets + // divided by 6. + if (mask & 0x4 && suq->tex.target.isCube()) { + int d = util_bitcount(mask & 0x3); + bld.setPosition(suq, true); + bld.mkOp2(OP_DIV, TYPE_U32, suq->getDef(d), suq->getDef(d), + bld.loadImm(NULL, 6)); + } + + // Samples come from a different query. If we want both samples and dims, + // create a second suq. + if (mask & 0x8) { + int d = util_bitcount(mask & 0x7); + Value *dst = suq->getDef(d); + TexInstruction *samples = suq; + assert(dst); + + if (mask != 0x8) { + suq->setDef(d, NULL); + suq->tex.mask &= 0x7; + samples = cloneShallow(func, suq); + for (int i = 0; i < d; i++) + samples->setDef(d, NULL); + samples->setDef(0, dst); + suq->bb->insertAfter(suq, samples); + } + samples->tex.mask = 0x4; + samples->tex.query = TXQ_TYPE; + } + + return true; +} + +bool NVC0LoweringPass::handleSUQ(TexInstruction *suq) { int mask = suq->tex.mask; @@ -2912,7 +2968,10 @@ NVC0LoweringPass::visit(Instruction *i) handleSurfaceOpNVC0(i->asTex()); break; case OP_SUQ: - handleSUQ(i->asTex()); + if (targ->getChipset() >= NVISA_GM107_CHIPSET) + handleSUQGM107(i->asTex()); + else + handleSUQ(i->asTex()); break; case OP_BUFQ: handleBUFQ(i); diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h index 37d52976657..8adff8817f5 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h @@ -107,6 +107,7 @@ protected: virtual bool handleManualTXD(TexInstruction *); bool handleTXLQ(TexInstruction *); bool handleSUQ(TexInstruction *); + bool handleSUQGM107(TexInstruction *); bool handleATOM(Instruction *); bool handleCasExch(Instruction *, bool needCctl); void handleSurfaceOpGM107(TexInstruction *); -- 2.13.6 _______________________________________________ mesa-dev mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-dev
