From: Dave Airlie <airl...@redhat.com>
This moves the lds_size calcs into the shader so we have all
the size stuff in one file.
Signed-off-by: Dave Airlie <airl...@redhat.com>
---
src/amd/common/ac_nir_to_llvm.c | 33 +++++++++++++++++++++++++++++++++
src/amd/common/ac_nir_to_llvm.h | 1 +
src/amd/vulkan/radv_pipeline.c | 30 ++++--------------------------
3 files changed, 38 insertions(+), 26 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index c235c5314be..1cf181ddeba 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -357,6 +357,38 @@ get_tcs_num_patches(struct radv_shader_context *ctx)
return num_patches;
}
+static unsigned
+calculate_tess_lds_size(struct radv_shader_context *ctx)
+{
+ unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
+ unsigned num_tcs_output_cp;
+ unsigned num_tcs_outputs, num_tcs_patch_outputs;
+ unsigned input_vertex_size, output_vertex_size;
+ unsigned input_patch_size, output_patch_size;
+ unsigned pervertex_output_patch_size;
+ unsigned output_patch0_offset;
+ unsigned num_patches;
+ unsigned lds_size;
+
+ num_tcs_output_cp = ctx->tcs_vertices_per_patch;
+ num_tcs_outputs =
util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
+ num_tcs_patch_outputs =
util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
+
+ input_vertex_size = ctx->tcs_num_inputs * 16;
+ output_vertex_size = num_tcs_outputs * 16;
+
+ input_patch_size = num_tcs_input_cp * input_vertex_size;
+
+ pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
+ output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs
* 16;
+
+ num_patches = ctx->tcs_num_patches;
+ output_patch0_offset = input_patch_size * num_patches;
+
+ lds_size = output_patch0_offset + output_patch_size * num_patches;
+ return lds_size;
+}
+
/* Tessellation shaders pass outputs to the next shader using LDS.
*
* LS outputs = TCS inputs
@@ -6981,6 +7013,7 @@ LLVMModuleRef
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
shaders[i]->info.gs.vertices_out;
} else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
shader_info->tcs.num_patches = ctx.tcs_num_patches;
+ shader_info->tcs.lds_size =
calculate_tess_lds_size(&ctx);
}
}
diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h
index 62ce72fb7d2..f4825ef4cd5 100644
--- a/src/amd/common/ac_nir_to_llvm.h
+++ b/src/amd/common/ac_nir_to_llvm.h
@@ -199,6 +199,7 @@ struct ac_shader_variant_info {
unsigned tcs_vertices_out;
/* Which outputs are actually written */
uint32_t num_patches;
+ uint32_t lds_size;
} tcs;
struct {
struct ac_vs_output_info outinfo;
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 195daf6abde..e9a9ae975b1 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1306,39 +1306,17 @@ static struct radv_tessellation_state
calculate_tess_state(struct radv_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo)
{
- unsigned num_tcs_input_cp =
pCreateInfo->pTessellationState->patchControlPoints;
- unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
- unsigned num_tcs_patch_outputs;
- unsigned input_vertex_size, output_vertex_size,
pervertex_output_patch_size;
- unsigned input_patch_size, output_patch_size, output_patch0_offset;
+ unsigned num_tcs_input_cp;
+ unsigned num_tcs_output_cp;
unsigned lds_size;
unsigned num_patches;
struct radv_tessellation_state tess = {0};
- /* This calculates how shader inputs and outputs among VS, TCS, and TES
- * are laid out in LDS. */
- num_tcs_inputs =
util_last_bit64(radv_get_vertex_shader(pipeline)->info.info.vs.ls_outputs_written);
- num_tcs_outputs =
util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
//tcs->outputs_written
+ num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
num_tcs_output_cp =
pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS
VERTICES OUT
- num_tcs_patch_outputs =
util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.patch_outputs_written);
-
- /* Ensure that we only need one wave per SIMD so we don't need to check
- * resource usage. Also ensures that the number of tcs in and out
- * vertices per threadgroup are at most 256.
- */
- input_vertex_size = num_tcs_inputs * 16;
- output_vertex_size = num_tcs_outputs * 16;
-
- input_patch_size = num_tcs_input_cp * input_vertex_size;
-
- pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
- output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs
* 16;
-
num_patches =
pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
- output_patch0_offset = input_patch_size * num_patches;
- /* perpatch_output_offset = output_patch0_offset +
pervertex_output_patch_size;*/
- lds_size = output_patch0_offset + output_patch_size * num_patches;
+ lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
assert(lds_size <= 65536);
--
2.14.3
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