On Tue, Mar 6, 2018 at 11:28 AM, Ian Romanick <i...@freedesktop.org> wrote:
> On 03/06/2018 11:24 AM, Matt Turner wrote:
>> On Tue, Mar 6, 2018 at 11:22 AM, Ian Romanick <i...@freedesktop.org> wrote:
>>> On 03/05/2018 04:40 PM, Matt Turner wrote:
>>>> On Fri, Feb 23, 2018 at 3:56 PM, Ian Romanick <i...@freedesktop.org> wrote:
>>>>> From: Kenneth Graunke <kenn...@whitecape.org>
>>>>> v2 (idr): Don't allow CSEL with a non-float src2.
>>>>> v3 (idr): Add CSEL to fs_inst::flags_written. Suggested by Matt.
>>> Do we need to update vec4 code? This instruction is BDW+, and we don't
>>> use the vec4 backend for anything on those platforms... and this
>>> optimization is FS-only.
>> Not strictly necessary, but those conditions are checking the same
>> thing so I'd keep them in sync.
> Ok. How can I test various dump_instruction and brw_disassemble_inst paths?
brw_disassemble_inst() is called when we use INTEL_DEBUG=fs,vs,gs,etc
to disassemble individual instructions. INTEL_DEBUG=... on a shader
with csel without the change to brw_disassemble_inst should print
csel.cmod.f0, and with the change should just print csel.cmod.
dump_instructions() prints the backend IR and is used for debugging
optimization passes. INTEL_DEBUG=optimizer will write out text files
after each optimization pass that makes progress. The change will
prevent the .f0 from being printed, like in brw_disassemble_inst().
We don't want to print .f0 because it doesn't write (or even use!) .f0.
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