This requires us to bump the subgroup size to 32 for all shader stages
because Vulkan requires that to be a physical device query.
Reviewed-by: Iago Toral Quiroga <ito...@igalia.com>
---
src/intel/compiler/brw_compiler.h | 8 ++++++++
src/intel/compiler/brw_nir.c | 3 +--
src/intel/vulkan/anv_device.c | 24 ++++++++++++++++++++++++
src/intel/vulkan/anv_pipeline.c | 6 ++++++
4 files changed, 39 insertions(+), 2 deletions(-)
diff --git a/src/intel/compiler/brw_compiler.h
b/src/intel/compiler/brw_compiler.h
index d8287dc..0e27c89 100644
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -113,6 +113,14 @@ struct brw_compiler {
bool supports_pull_constants;
};
+/**
+ * We use a constant subgroup size of 32. It really only needs to be a
+ * maximum and, since we do SIMD32 for compute shaders in some cases, it
+ * needs to be at least 32. SIMD8 and SIMD16 shaders will still claim a
+ * subgroup size of 32 but will act as if 16 or 24 of those channels are
+ * disabled.
+ */
+#define BRW_SUBGROUP_SIZE 32
/**
* Program key structures.
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index dbad4a1..69ab162 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -650,8 +650,7 @@ brw_preprocess_nir(const struct brw_compiler *compiler,
nir_shader *nir)
OPT(nir_lower_system_values);
const nir_lower_subgroups_options subgroups_options = {
- .subgroup_size = nir->info.stage == MESA_SHADER_COMPUTE ? 32 :
- nir->info.stage == MESA_SHADER_FRAGMENT ? 16 : 8,
+ .subgroup_size = BRW_SUBGROUP_SIZE,
.ballot_bit_size = 32,
.lower_to_scalar = true,
.lower_subgroup_masks = true,
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 57316e4..d8c4e98 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1042,6 +1042,30 @@ void anv_GetPhysicalDeviceProperties2(
break;
}
+ case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
+ VkPhysicalDeviceSubgroupProperties *properties = (void *)ext;
+
+ properties->subgroupSize = BRW_SUBGROUP_SIZE;
+
+ VkShaderStageFlags scalar_stages = 0;
+ for (unsigned stage = 0; stage < MESA_SHADER_STAGES; stage++) {
+ if (pdevice->compiler->scalar_stage[stage])
+ scalar_stages |= mesa_to_vk_shader_stage(stage);
+ }
+ properties->supportedStages = scalar_stages;
+
+ properties->supportedOperations = VK_SUBGROUP_FEATURE_BASIC_BIT |
+ VK_SUBGROUP_FEATURE_VOTE_BIT |
+ VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
+ VK_SUBGROUP_FEATURE_BALLOT_BIT |
+ VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
+
VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT |
+ VK_SUBGROUP_FEATURE_CLUSTERED_BIT |
+ VK_SUBGROUP_FEATURE_QUAD_BIT;
+ properties->quadOperationsInAllStages = VK_TRUE;
+ break;
+ }
+
default:
anv_debug_ignored_stype(ext->sType);
break;
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index f25cf37..9cfd16d 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -144,6 +144,12 @@ anv_shader_compile_to_nir(struct anv_pipeline *pipeline,
.multiview = true,
.variable_pointers = true,
.storage_16bit = device->instance->physicalDevice.info.gen >= 8,
+ .subgroup_arithmetic = true,
+ .subgroup_basic = true,
+ .subgroup_ballot = true,
+ .subgroup_quad = true,
+ .subgroup_shuffle = true,
+ .subgroup_vote = true,
},
};
--
2.5.0.400.gff86faf
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