On Wed, Mar 7, 2018 at 3:34 PM, Marek Olšák <mar...@gmail.com> wrote:
> From: Marek Olšák <marek.ol...@amd.com>
>
> ---
>  src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
> b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
> index d9a95c0..9cd3343 100644
> --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
> +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
> @@ -1531,20 +1531,24 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs 
> *rcs,
>        /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
>        if (ws->info.gfx_ib_pad_with_type2) {
>           while (rcs->current.cdw & 7)
>              radeon_emit(rcs, 0x80000000); /* type2 nop packet */
>        } else {
>           while (rcs->current.cdw & 7)
>              radeon_emit(rcs, 0xffff1000); /* type3 nop packet */
>        }
>        ws->gfx_ib_size_counter += (rcs->prev_dw + rcs->current.cdw) * 4;
>        break;
> +   case RING_COMPUTE:
> +      while (rcs->current.cdw & 7)
> +         radeon_emit(rcs, 0xffff1000); /* type3 nop packet */
> +      break;

This only works on CIK I think.  SI might still require type2 packets.

Alex

>     case RING_UVD:
>     case RING_UVD_ENC:
>        while (rcs->current.cdw & 15)
>           radeon_emit(rcs, 0x80000000); /* type2 nop packet */
>        break;
>     case RING_VCN_DEC:
>        while (rcs->current.cdw & 15)
>           radeon_emit(rcs, 0x81ff); /* nop packet */
>        break;
>     default:
> --
> 2.7.4
>
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