Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
for the series.
On Wed, Mar 21, 2018 at 9:30 PM, Samuel Pitoiset
<samuel.pitoi...@gmail.com> wrote:
> The hardware only supports 32-bit depth surfaces, but we can
> enable TC-compat HTILE for 16-bit depth surfaces if no Z planes
> are compressed.
>
> The main benefit is to reduce the number of depth decompression
> passes. Also, we don't need to implement DB->CB copies which is
> fine.
>
> This improves Serious Sam 2017 by +4%. Talos and F12017 are also
> affected but I don't see a performance difference.
>
> This also improves the shadowmapping Vulkan demo by 10-15%
> (FPS is now similar to AMDVLK).
>
> No CTS regressions on Polaris10.
>
> Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
> ---
> src/amd/vulkan/radv_device.c | 22 ++++++++++++++++------
> src/amd/vulkan/radv_image.c | 20 ++++++++------------
> 2 files changed, 24 insertions(+), 18 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> index 22500bfc13..9c82fd059f 100644
> --- a/src/amd/vulkan/radv_device.c
> +++ b/src/amd/vulkan/radv_device.c
> @@ -3615,12 +3615,22 @@ radv_calc_decompress_on_z_planes(struct radv_device
> *device,
>
> max_zplanes = max_zplanes + 1;
> } else {
> - if (iview->image->info.samples <= 1)
> - max_zplanes = 5;
> - else if (iview->image->info.samples <= 4)
> - max_zplanes = 3;
> - else
> - max_zplanes = 2;
> + if (iview->vk_format == VK_FORMAT_D16_UNORM) {
> + /* Do not enable Z plane compression for 16-bit depth
> + * surfaces because isn't supported on GFX8. Only
> + * 32-bit depth surfaces are supported by the
> hardware.
> + * This allows to maintain shader compatibility and to
> + * reduce the number of depth decompressions.
> + */
> + max_zplanes = 1;
> + } else {
> + if (iview->image->info.samples <= 1)
> + max_zplanes = 5;
> + else if (iview->image->info.samples <= 4)
> + max_zplanes = 3;
> + else
> + max_zplanes = 2;
> + }
> }
>
> return max_zplanes;
> diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
> index 6e5f3e7ad0..dd3189c67d 100644
> --- a/src/amd/vulkan/radv_image.c
> +++ b/src/amd/vulkan/radv_image.c
> @@ -91,18 +91,14 @@ radv_image_is_tc_compat_htile(struct radv_device *device,
> pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT)
> return false;
>
> - if (device->physical_device->rad_info.chip_class >= GFX9) {
> - /* GFX9 supports both 32-bit and 16-bit depth surfaces. */
> - if (pCreateInfo->format != VK_FORMAT_D32_SFLOAT_S8_UINT &&
> - pCreateInfo->format != VK_FORMAT_D32_SFLOAT &&
> - pCreateInfo->format != VK_FORMAT_D16_UNORM)
> - return false;
> - } else {
> - /* GFX8 only supports 32-bit depth surfaces. */
> - if (pCreateInfo->format != VK_FORMAT_D32_SFLOAT_S8_UINT &&
> - pCreateInfo->format != VK_FORMAT_D32_SFLOAT)
> - return false;
> - }
> + /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8
> only
> + * supports 32-bit. Though, it's possible to enable TC-compat for
> + * 16-bit depth surfaces if no Z planes are compressed.
> + */
> + if (pCreateInfo->format != VK_FORMAT_D32_SFLOAT_S8_UINT &&
> + pCreateInfo->format != VK_FORMAT_D32_SFLOAT &&
> + pCreateInfo->format != VK_FORMAT_D16_UNORM)
> + return false;
>
> return true;
> }
> --
> 2.16.2
>
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