After giving it some thought, I don't think this patch is quite strong enough to fix the real bug. The problem isn't that we're reswizzling a register. The problem is that we're trying to coalesce something like
ssa_1 = fadd r1, r2 /* Some stuff */ r3 = vec4(ssa_1, ssa_1.y, ...) coalescing this together moves the write to r3 up to the fadd even though there may have been other writes to r3 in between. None the less, very good job tracking this down! :-) --Jason On Thu, Mar 22, 2018 at 4:30 AM, vadym.shovkoplias < vadim.shovkopl...@gmail.com> wrote: > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105440 > Fixes: 2458ea95c56 "nir/lower_vec_to_movs: Coalesce movs on-the-fly when > possible" > Signed-off-by: Andriy Khulap <andriy.khu...@globallogic.com> > Signed-off-by: Vadym Shovkoplias <vadym.shovkopl...@globallogic.com> > --- > src/compiler/nir/nir_lower_vec_to_movs.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/src/compiler/nir/nir_lower_vec_to_movs.c > b/src/compiler/nir/nir_lower_vec_to_movs.c > index 711ddd3..4758f7d 100644 > --- a/src/compiler/nir/nir_lower_vec_to_movs.c > +++ b/src/compiler/nir/nir_lower_vec_to_movs.c > @@ -166,9 +166,14 @@ try_coalesce(nir_alu_instr *vec, unsigned start_idx) > /* If we are going to reswizzle the instruction, we can't have any > * non-per-component sources either. > */ > - for (unsigned j = 0; j < nir_op_infos[src_alu->op].num_inputs; j++) > + for (unsigned j = 0; j < nir_op_infos[src_alu->op].num_inputs; > j++) { > if (nir_op_infos[src_alu->op].input_sizes[j] != 0) > return 0; > + > + /* Don't coalesce the mmove when src and dest are the same reg */ > + if (src_matches_dest_reg(&vec->dest.dest, &src_alu->src[j].src)) > + return 0; > + } > } > > /* Stash off all of the ALU instruction's swizzles. */ > -- > 2.7.4 > > _______________________________________________ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev >
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