On Fri, Mar 23, 2018 at 11:35 AM, Jason Ekstrand <ja...@jlekstrand.net> wrote: > Otherwise we may end up trying to coalesce in a case such as > > ssa_1 = fadd r1, r2 > r3.x = fneg(r2); > r3 = vec4(ssa_1, ssa_1.y, ...) > > and that would cause us to move the writes to r3 from the vec to the > fadd which would re-order them with respect to the write from the fneg. > In order to solve this, we just don't coalesce if the destination of the > vec is not SSA. We could try to get clever and still coalesce if there > are no writes to the destination of the vec between the vec and the ALU > source. However, since registers only come from phi webs and indirects, > the chances of having a vec with a register destination that is actually > coalescable into its source is very slim. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105440 > Fixes: 2458ea95c56 "nir/lower_vec_to_movs: Coalesce movs on-the-fly when > possible" > Reported-by: Vadym Shovkoplias <vadym.shovkopl...@globallogic.com> > Cc: Andriy Khulap <andriy.khu...@globallogic.com> > Cc: Vadym Shovkoplias <vadym.shovkopl...@globallogic.com>
Awesome. Very glad to see that bug solved! Reviewed-by: Matt Turner <matts...@gmail.com> I'll be interested to hear if this fixed anything else from the shader-db results. _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev