From: Marek Olšák <[email protected]>
---
src/amd/common/ac_gpu_info.c | 2 ++
src/amd/common/ac_gpu_info.h | 1 +
src/gallium/drivers/radeonsi/si_clear.c | 7 ++-----
src/gallium/drivers/radeonsi/si_texture.c | 6 ++----
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 3 +++
5 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index b1022ef75de..d9b5b4a1960 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -310,20 +310,21 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
uvd_enc.available_rings ? true : false;
info->has_userptr = true;
info->has_syncobj = has_syncobj(fd);
info->has_syncobj_wait_for_submit = info->has_syncobj &&
info->drm_minor >= 20;
info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
info->has_ctx_priority = info->drm_minor >= 22;
/* TODO: Enable this once the kernel handles it efficiently. */
info->has_local_buffers = info->drm_minor >= 20 &&
!info->has_dedicated_vram;
info->kernel_flushes_hdp_before_ib = true;
+ info->htile_cmask_support_1d_tiling = true;
info->num_render_backends = amdinfo->rb_pipes;
/* The value returned by the kernel driver was wrong. */
if (info->family == CHIP_KAVERI)
info->num_render_backends = 2;
info->clock_crystal_freq = amdinfo->gpu_counter_freq;
if (!info->clock_crystal_freq) {
fprintf(stderr, "amdgpu: clock crystal frequency is 0,
timestamps will be wrong\n");
info->clock_crystal_freq = 1;
@@ -458,20 +459,21 @@ void ac_print_gpu_info(struct radeon_info *info)
printf("Kernel info:\n");
printf(" drm = %i.%i.%i\n", info->drm_major,
info->drm_minor, info->drm_patchlevel);
printf(" has_userptr = %i\n", info->has_userptr);
printf(" has_syncobj = %u\n", info->has_syncobj);
printf(" has_syncobj_wait_for_submit = %u\n",
info->has_syncobj_wait_for_submit);
printf(" has_fence_to_handle = %u\n", info->has_fence_to_handle);
printf(" has_ctx_priority = %u\n", info->has_ctx_priority);
printf(" has_local_buffers = %u\n", info->has_local_buffers);
printf(" kernel_flushes_hdp_before_ib = %u\n",
info->kernel_flushes_hdp_before_ib);
+ printf(" htile_cmask_support_1d_tiling = %u\n",
info->htile_cmask_support_1d_tiling);
printf("Shader core info:\n");
printf(" max_shader_clock = %i\n", info->max_shader_clock);
printf(" num_good_compute_units = %i\n",
info->num_good_compute_units);
printf(" max_se = %i\n", info->max_se);
printf(" max_sh_per_se = %i\n", info->max_sh_per_se);
printf("Render backend info:\n");
printf(" num_render_backends = %i\n", info->num_render_backends);
printf(" num_tile_pipes = %i\n", info->num_tile_pipes);
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 8a9721750a6..578c3fb7da1 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -90,20 +90,21 @@ struct radeon_info {
uint32_t drm_major; /* version */
uint32_t drm_minor;
uint32_t drm_patchlevel;
bool has_userptr;
bool has_syncobj;
bool has_syncobj_wait_for_submit;
bool has_fence_to_handle;
bool has_ctx_priority;
bool has_local_buffers;
bool kernel_flushes_hdp_before_ib;
+ bool htile_cmask_support_1d_tiling;
/* Shader cores. */
uint32_t r600_max_quad_pipes; /* wave size / 16 */
uint32_t max_shader_clock;
uint32_t num_good_compute_units;
uint32_t max_se; /* shader engines */
uint32_t max_sh_per_se; /* shader arrays per shader
engine */
/* Render backends (color + depth blocks). */
uint32_t r300_num_gb_pipes;
diff --git a/src/gallium/drivers/radeonsi/si_clear.c
b/src/gallium/drivers/radeonsi/si_clear.c
index 23977186611..0e2d2f1013b 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -430,27 +430,24 @@ static void si_do_fast_color_clear(struct si_context
*sctx,
}
/* shared textures can't use fast clear without an explicit
flush,
* because there is no way to communicate the clear color among
* all clients
*/
if (tex->buffer.b.is_shared &&
!(tex->buffer.external_usage &
PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
continue;
- /* fast color clear with 1D tiling doesn't work on old kernels
and CIK */
- if (sctx->chip_class == CIK &&
+ if (sctx->chip_class <= VI &&
tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D
&&
- sctx->screen->info.drm_major == 2 &&
- sctx->screen->info.drm_minor < 38) {
+ !sctx->screen->info.htile_cmask_support_1d_tiling)
continue;
- }
/* Fast clear is the most appropriate place to enable DCC for
* displayable surfaces.
*/
if (sctx->chip_class >= VI &&
!(sctx->screen->debug_flags & DBG(NO_DCC_FB))) {
vi_separate_dcc_try_enable(sctx, tex);
/* RB+ isn't supported with a CMASK clear only on
Stoney,
* so all clears are considered to be hypothetically
slow
diff --git a/src/gallium/drivers/radeonsi/si_texture.c
b/src/gallium/drivers/radeonsi/si_texture.c
index 0ebe8d31bed..f38d4721331 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -915,24 +915,22 @@ static void si_texture_get_htile_size(struct si_screen
*sscreen,
struct r600_texture *rtex)
{
unsigned cl_width, cl_height, width, height;
unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
unsigned num_pipes = sscreen->info.num_tile_pipes;
assert(sscreen->info.chip_class <= VI);
rtex->surface.htile_size = 0;
- /* HTILE is broken with 1D tiling on old kernels and CIK. */
- if (sscreen->info.chip_class >= CIK &&
- rtex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
- sscreen->info.drm_major == 2 && sscreen->info.drm_minor < 38)
+ if (rtex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
+ !sscreen->info.htile_cmask_support_1d_tiling)
return;
/* Overalign HTILE on P2 configs to work around GPU hangs in
* piglit/depthstencil-render-miplevels 585.
*
* This has been confirmed to help Kabini & Stoney, where the hangs
* are always reproducible. I think I have seen the test hang
* on Carrizo too, though it was very rare there.
*/
if (sscreen->info.chip_class >= CIK && num_pipes < 4)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index ab6cc60597d..d0d7e15803b 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -526,20 +526,23 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
/* Hawaii with old firmware needs type2 nop packet.
* accel_working2 with value 3 indicates the new firmware.
*/
ws->info.gfx_ib_pad_with_type2 = ws->info.chip_class <= SI ||
(ws->info.family == CHIP_HAWAII &&
ws->accel_working2 < 3);
ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */
ws->info.ib_start_alignment = 4096;
ws->info.kernel_flushes_hdp_before_ib = ws->info.drm_minor >= 40;
+ /* HTILE is broken with 1D tiling on old kernels and CIK. */
+ ws->info.htile_cmask_support_1d_tiling = ws->info.chip_class != CIK ||
+ ws->info.drm_minor >= 38;
ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") !=
NULL;
return true;
}
static void radeon_winsys_destroy(struct radeon_winsys *rws)
{
struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
--
2.17.0
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