From: Francisco Jerez <curroje...@riseup.net>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/intel/compiler/brw_fs.cpp | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index f583900..ae59716 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -5088,8 +5088,14 @@ get_fpu_lowered_simd_width(const struct gen_device_info
*devinfo,
type_sz(inst->dst.type) == 4 && inst->dst.stride == 1 &&
type_sz(inst->src[i].type) == 2 && inst->src[i].stride == 1;
+ /* We check size_read(i) against size_written instead of REG_SIZE
+ * because we want to properly handle SIMD32. In SIMD32, you can end
+ * up which writes 4 registers and a source that reads 2 registers
+ * and we may still need to lower all the way to SIMD8 in that case.
+ */
if (inst->size_written > REG_SIZE &&
- inst->size_read(i) != 0 && inst->size_read(i) <= REG_SIZE &&
+ inst->size_read(i) != 0 &&
+ inst->size_read(i) < inst->size_written &&
!is_scalar_exception && !is_packed_word_exception) {
const unsigned reg_count = DIV_ROUND_UP(inst->size_written,
REG_SIZE);
max_width = MIN2(max_width, inst->exec_size / reg_count);
--
2.5.0.400.gff86faf
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
