We previously retiled miptrees to work around limitations of the BLT engine. BLORP fallbacks can overcome these, so we no longer have need for retiling.
Removing retiling fixes a number of problems. If the row pitch was too wide for the BLT engine, we retiled to linear and had the following issues: * We retiled on gen6+ platforms which don't actually use the blitter. * We ignored miptree_create_for_bo's requests for tiled miptrees. I don't know how to write a test for the last issue unfortunately. Also, I haven't nominated this for stable releases, because of the amount of churn needed - we'd have to pull in the series which stops using the blitter on gen6+. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106738 --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 62 +------------------ 1 file changed, 1 insertion(+), 61 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 1c888d5210b..a57720b338a 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -509,46 +509,6 @@ free_aux_state_map(enum isl_aux_state **state) free(state); } -static bool -need_to_retile_as_linear(struct brw_context *brw, unsigned row_pitch, - enum isl_tiling tiling, unsigned samples) -{ - if (samples > 1) - return false; - - if (tiling == ISL_TILING_LINEAR) - return false; - - /* If the width is much smaller than a tile, don't bother tiling. */ - if (row_pitch < 64) - return true; - - if (ALIGN(row_pitch, 512) >= 32768) { - perf_debug("row pitch %u too large to blit, falling back to untiled", - row_pitch); - return true; - } - - return false; -} - -static bool -need_to_retile_as_x(const struct brw_context *brw, uint64_t size, - enum isl_tiling tiling) -{ - const struct gen_device_info *devinfo = &brw->screen->devinfo; - - /* If the BO is too large to fit in the aperture, we need to use the - * BLT engine to support it. Prior to Sandybridge, the BLT paths can't - * handle Y-tiling, so we need to fall back to X. - */ - if (devinfo->gen < 6 && size >= brw->max_gtt_map_object_size && - tiling == ISL_TILING_Y0) - return true; - - return false; -} - static struct intel_mipmap_tree * make_surface(struct brw_context *brw, GLenum target, mesa_format format, unsigned first_level, unsigned last_level, @@ -580,7 +540,7 @@ make_surface(struct brw_context *brw, GLenum target, mesa_format format, num_samples, width0, height0, depth0, first_level, last_level, mt); - struct isl_surf_init_info init_info = { + const struct isl_surf_init_info init_info = { .dim = get_isl_surf_dim(target), .format = translate_tex_format(brw, format, false), .width = width0, @@ -597,26 +557,6 @@ make_surface(struct brw_context *brw, GLenum target, mesa_format format, if (!isl_surf_init_s(&brw->isl_dev, &mt->surf, &init_info)) goto fail; - /* Depth surfaces are always Y-tiled and stencil is always W-tiled, although - * on gen7 platforms we also need to create Y-tiled copies of stencil for - * texturing since the hardware can't sample from W-tiled surfaces. For - * everything else, check for corner cases needing special treatment. - */ - bool is_depth_stencil = - mt->surf.usage & (ISL_SURF_USAGE_STENCIL_BIT | ISL_SURF_USAGE_DEPTH_BIT); - if (!is_depth_stencil) { - if (need_to_retile_as_linear(brw, mt->surf.row_pitch, - mt->surf.tiling, mt->surf.samples)) { - init_info.tiling_flags = 1u << ISL_TILING_LINEAR; - if (!isl_surf_init_s(&brw->isl_dev, &mt->surf, &init_info)) - goto fail; - } else if (need_to_retile_as_x(brw, mt->surf.size, mt->surf.tiling)) { - init_info.tiling_flags = 1u << ISL_TILING_X; - if (!isl_surf_init_s(&brw->isl_dev, &mt->surf, &init_info)) - goto fail; - } - } - /* In case of linear the buffer gets padded by fixed 64 bytes and therefore * the size may not be multiple of row_pitch. * See isl_apply_surface_padding(). -- 2.17.0 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
