On Tue, 2018-06-05 at 11:39 -0400, Rob Clark wrote: > On Tue, Jun 5, 2018 at 10:38 AM, Philipp Zabel <[email protected]> wrote: > > Since all threads share a global temporary vec4 register file, it is > > important to reduce temporary register use of shaders. > > Using source swizzles and destination write mask of ALU operations we > > can layer smaller virtual registers on top of the physical base > > registers that overlap with their base register and partially with each > > other: > > > > +----+---------+-------------+---------+ > > |VEC4| VEC3 | VEC2 | SCALAR | > > +----+---------+-------------+---------+ > > | X | X X X | X X X | X | > > | Y | Y Y Y | Y Y Y | Y | > > | Z | Z Z Z | Z Z Z | Z | > > | W | W W W | W W W | W | > > +----+---------+-------------+---------+ > > > > There are four possible virtual vec3 registers that leave the remaining > > component usable as a scalar virtual register, six possible vec2 > > registers, and four possible scalar registers that only use a single > > component. > > > > This patch adds an interference graph for virtual registers to the > > register allocator, using information about SSA interference and virtual > > register overlap. If possible, SSAs with smaller num_components are > > allocated from the unused components of already partially used temporary > > registers. > > > > Signed-off-by: Philipp Zabel <[email protected]> > > Signed-off-by: Michael Tretter <[email protected]> > > --- > > so one quick note, constructing the register classes can be > expensive.. you probably only want to do this once and then re-use for > each shader
Thank you. Yes, that should be easily fixable. The main reason we haven't already done this is that I hadn't added the dummy RA node that grabs the forbidden register 0 in fragment shaders until the last minute. Previously we had left out the register from the graph altogether. regards Philipp _______________________________________________ mesa-dev mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-dev
