From: Marek Olšák <marek.ol...@amd.com>
The change from MIN2 to MAX2 is intentional.
---
src/amd/common/ac_gpu_info.c | 82 ++++++++++++++++++++++++------------
1 file changed, 54 insertions(+), 28 deletions(-)
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 6bee96b9eee..3b6600dcbc6 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -91,21 +91,20 @@ static bool has_syncobj(int fd)
return false;
return value ? true : false;
}
bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
struct radeon_info *info,
struct amdgpu_gpu_info *amdinfo)
{
struct drm_amdgpu_info_device device_info = {};
struct amdgpu_buffer_size_alignments alignment_info = {};
- struct amdgpu_heap_info vram, vram_vis, gtt;
struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {};
struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {};
struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {};
struct amdgpu_gds_resource_info gds = {};
uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature
= 0;
int r, i, j;
drmDevicePtr devinfo;
/* Get PCI info. */
r = drmGetDevice2(fd, 0, &devinfo);
@@ -132,40 +131,20 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
fprintf(stderr, "amdgpu: amdgpu_query_info(dev_info)
failed.\n");
return false;
}
r = amdgpu_query_buffer_size_alignment(dev, &alignment_info);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment
failed.\n");
return false;
}
- r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
- if (r) {
- fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram)
failed.\n");
- return false;
- }
-
- r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM,
- AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
- &vram_vis);
- if (r) {
- fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram_vis)
failed.\n");
- return false;
- }
-
- r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_GTT, 0, >t);
- if (r) {
- fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt)
failed.\n");
- return false;
- }
-
r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_DMA, 0, &dma);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(dma)
failed.\n");
return false;
}
r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_GFX, 0, &gfx);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(gfx)
failed.\n");
return false;
@@ -256,20 +235,74 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
fprintf(stderr, "amdgpu: amdgpu_query_sw_info(address32_hi)
failed.\n");
return false;
}
r = amdgpu_query_gds_info(dev, &gds);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_gds_info failed.\n");
return false;
}
+ if (info->drm_minor >= 9) {
+ struct drm_amdgpu_memory_info meminfo;
+
+ r = amdgpu_query_info(dev, AMDGPU_INFO_MEMORY, sizeof(meminfo),
&meminfo);
+ if (r) {
+ fprintf(stderr, "amdgpu: amdgpu_query_info(memory)
failed.\n");
+ return false;
+ }
+
+ /* Note: usable_heap_size values can be random and can't be
relied on. */
+ info->gart_size = meminfo.gtt.total_heap_size;
+ info->vram_size = meminfo.vram.total_heap_size;
+ info->vram_vis_size =
meminfo.cpu_accessible_vram.total_heap_size;
+
+ info->max_alloc_size = MAX2(meminfo.vram.max_allocation,
+ meminfo.gtt.max_allocation);
+ } else {
+ /* This is a deprecated interface, which reports usable sizes
+ * (total minus pinned), but the pinned size computation is
+ * buggy, so the values returned from these functions can be
+ * random.
+ */
+ struct amdgpu_heap_info vram, vram_vis, gtt;
+
+ r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 0,
&vram);
+ if (r) {
+ fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram)
failed.\n");
+ return false;
+ }
+
+ r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM,
+ AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
+ &vram_vis);
+ if (r) {
+ fprintf(stderr, "amdgpu:
amdgpu_query_heap_info(vram_vis) failed.\n");
+ return false;
+ }
+
+ r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_GTT, 0, >t);
+ if (r) {
+ fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt)
failed.\n");
+ return false;
+ }
+
+ info->gart_size = gtt.heap_size;
+ info->vram_size = vram.heap_size;
+ info->vram_vis_size = vram_vis.heap_size;
+
+ /* The kernel can split large buffers in VRAM but not in GTT,
so large
+ * allocations can fail or cause buffer movement failures in
the kernel.
+ */
+ info->max_alloc_size = MAX2(info->vram_size * 0.9,
info->gart_size * 0.7);
+ }
+
/* Set chip identification. */
info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */
info->vce_harvest_config = amdinfo->vce_harvest_config;
switch (info->pci_id) {
#define CHIPSET(pci_id, cfamily) case pci_id: info->family = CHIP_##cfamily;
break;
#include "pci_ids/radeonsi_pci_ids.h"
#undef CHIPSET
default:
@@ -288,29 +321,22 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
else {
fprintf(stderr, "amdgpu: Unknown family.\n");
return false;
}
/* Set which chips have dedicated VRAM. */
info->has_dedicated_vram =
!(amdinfo->ids_flags & AMDGPU_IDS_FLAGS_FUSION);
/* Set hardware information. */
- info->gart_size = gtt.heap_size;
- info->vram_size = vram.heap_size;
- info->vram_vis_size = vram_vis.heap_size;
info->gds_size = gds.gds_total_size;
info->gds_gfx_partition_size = gds.gds_gfx_partition_size;
- /* The kernel can split large buffers in VRAM but not in GTT, so large
- * allocations can fail or cause buffer movement failures in the kernel.
- */
- info->max_alloc_size = MIN2(info->vram_size * 0.9, info->gart_size *
0.7);
/* convert the shader clock from KHz to MHz */
info->max_shader_clock = amdinfo->max_engine_clk / 1000;
info->num_tcc_blocks = device_info.num_tcc_blocks;
info->max_se = amdinfo->num_shader_engines;
info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
info->has_hw_decode =
(uvd.available_rings != 0) || (vcn_dec.available_rings != 0);
info->uvd_fw_version =
uvd.available_rings ? uvd_version : 0;
info->vce_fw_version =
--
2.17.1
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