From: Marek Olšák <marek.ol...@amd.com>
---
src/amd/common/ac_surface.c | 21 +++++++++++++++++++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 618b755afc7..6a335111314 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -429,20 +429,21 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib,
surf->htile_size = AddrHtileOut->htileBytes;
surf->htile_slice_size = AddrHtileOut->sliceSize;
surf->htile_alignment = AddrHtileOut->baseAlign;
}
}
return 0;
}
#define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
+#define V_009910_ADDR_SURF_THICK_MICRO_TILING 0x03
#define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
static void gfx6_set_micro_tile_mode(struct radeon_surf *surf,
const struct radeon_info *info)
{
uint32_t tile_mode =
info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
if (info->chip_class >= CIK)
surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
else
@@ -943,20 +944,31 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
surf->htile_size = (total_pixels / htile_block_size) *
htile_element_size;
surf->htile_size = align(surf->htile_size,
surf->htile_alignment);
}
surf->is_linear = surf->u.legacy.level[0].mode ==
RADEON_SURF_MODE_LINEAR_ALIGNED;
surf->is_displayable = surf->is_linear ||
surf->micro_tile_mode ==
RADEON_MICRO_MODE_DISPLAY ||
surf->micro_tile_mode ==
RADEON_MICRO_MODE_ROTATED;
+
+ /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
+ * used at the same time. This case is not currently expected to occur
+ * because we don't use rotated. Enforce this restriction on all chips
+ * to facilitate testing.
+ */
+ if (surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED) {
+ assert(!"rotate micro tile mode is unsupported");
+ return ADDR_ERROR;
+ }
+
return 0;
}
/* This is only called when expecting a tiled layout. */
static int
gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
bool is_fmask, unsigned flags,
AddrSwizzleMode *swizzle_mode)
{
@@ -1483,22 +1495,27 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
/* R = rotated. */
case ADDR_SW_256B_R:
case ADDR_SW_4KB_R:
case ADDR_SW_64KB_R:
case ADDR_SW_VAR_R:
case ADDR_SW_64KB_R_T:
case ADDR_SW_4KB_R_X:
case ADDR_SW_64KB_R_X:
case ADDR_SW_VAR_R_X:
- surf->micro_tile_mode = RADEON_MICRO_MODE_ROTATED;
- break;
+ /* The rotated micro tile mode doesn't work if both
CMASK and RB+ are
+ * used at the same time. This case is not currently
expected to occur
+ * because we don't use rotated. Enforce this
restriction on all chips
+ * to facilitate testing.
+ */
+ assert(!"rotate micro tile mode is unsupported");
+ return ADDR_ERROR;
/* Z = depth. */
case ADDR_SW_4KB_Z:
case ADDR_SW_64KB_Z:
case ADDR_SW_VAR_Z:
case ADDR_SW_64KB_Z_T:
case ADDR_SW_4KB_Z_X:
case ADDR_SW_64KB_Z_X:
case ADDR_SW_VAR_Z_X:
surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
--
2.17.1
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