Quoting Anuj Phogat (2018-08-28 18:53:59)
> h/w specification requires this bit to be always set.
>
> Suggested-by: Kenneth Graunke <kenn...@whitecape.org>
> Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
> ---
> src/mesa/drivers/dri/i965/brw_defines.h | 4 ++++
> src/mesa/drivers/dri/i965/brw_state_upload.c | 7 +++++++
> 2 files changed, 11 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
> b/src/mesa/drivers/dri/i965/brw_defines.h
> index 433314115b1..1c73ddeb190 100644
> --- a/src/mesa/drivers/dri/i965/brw_defines.h
> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> @@ -1673,6 +1673,10 @@ enum brw_pixel_shader_coverage_mask_mode {
> # define GLK_SCEC_BARRIER_MODE_3D_HULL (1 << 7)
> # define GLK_SCEC_BARRIER_MODE_MASK REG_MASK(1 << 7)
>
> +#define HALF_SLICE_CHICKEN7 0xE194
> +# define TEXEL_OFFSET_FIX_ENABLE (1 << 1)
> +# define TEXEL_OFFSET_FIX_MASK REG_MASK(1 << 7)
That mask doesn't match the enable-bit.
It'll probably be quite useful to record all the registers you are
setting as part of the global setup and read them back later to make
sure they stuck.
-Chris
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