This appears to hang broadwell; we should probably think twice before
enabling it so broadly. I'll adjust it to be gen9 only or we can just can
the patch entirely.
On Tue, Aug 21, 2018 at 8:58 PM Jason Ekstrand <ja...@jlekstrand.net> wrote:
> Known to fix nothing whatsoever but it's in the docs.
> ---
> src/intel/vulkan/genX_cmd_buffer.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/src/intel/vulkan/genX_cmd_buffer.c
> b/src/intel/vulkan/genX_cmd_buffer.c
> index 18f80e8d1bd..75b3dd54275 100644
> --- a/src/intel/vulkan/genX_cmd_buffer.c
> +++ b/src/intel/vulkan/genX_cmd_buffer.c
> @@ -1743,6 +1743,9 @@ genX(cmd_buffer_apply_pipe_flushes)(struct
> anv_cmd_buffer *cmd_buffer)
> }
>
> if (bits & ANV_PIPE_INVALIDATE_BITS) {
> + if (bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT)
> + anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe);
> +
> anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) {
> pipe.StateCacheInvalidationEnable =
> bits & ANV_PIPE_STATE_CACHE_INVALIDATE_BIT;
> @@ -1754,6 +1757,12 @@ genX(cmd_buffer_apply_pipe_flushes)(struct
> anv_cmd_buffer *cmd_buffer)
> bits & ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
> pipe.InstructionCacheInvalidateEnable =
> bits & ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT;
> +
> + if (pipe.VFCacheInvalidationEnable) {
> + pipe.PostSyncOperation = WriteImmediateData;
> + pipe.Address =
> + (struct anv_address) { &cmd_buffer->device->workaround_bo,
> 0 };
> + }
> }
>
> bits &= ~ANV_PIPE_INVALIDATE_BITS;
> --
> 2.17.1
>
>
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