Hi Dylan, this patch only matters for debug builds (DEBUG set), but your merge result looks correct nonetheless.
Thanks On Fri, Sep 14, 2018 at 6:16 PM, Dylan Baker <dy...@pnwbakers.com> wrote: > Quoting Pierre Moreau (2017-12-04 15:51:04) >> Those operations do not map to actual hardware instructions, therefore >> those should always be lowered to 32-bit instructions. >> >> Fixes: 009c54aa7af "nv50/ir: Split 64-bit integer MAD/MUL operations" >> Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> >> --- >> src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp >> b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp >> index 61d4e6a2d0..14bdcea2ca 100644 >> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp >> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp >> @@ -3794,7 +3794,7 @@ Program::optimizeSSA(int level) >> RUN_PASS(2, AlgebraicOpt, run); >> RUN_PASS(2, ModifierFolding, run); // before load propagation -> less >> checks >> RUN_PASS(1, ConstantFolding, foldAll); >> - RUN_PASS(1, Split64BitOpPreRA, run); >> + RUN_PASS(0, Split64BitOpPreRA, run); >> RUN_PASS(1, LoadPropagation, run); >> RUN_PASS(1, IndirectPropagation, run); >> RUN_PASS(2, MemoryOpt, run); >> -- >> 2.15.0 >> > > Hi Pierre, > > There was a small conflict when applying this to 18.1; I think my resolution > is > correct, but you can see the version of the patch here: > https://gitlab.freedesktop.org/mesa/mesa/commit/649aff1a8788684c3160ab6001016054de251f39 > please let me know if any changes are needed. > > Dylan > > _______________________________________________ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev > _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev