---
src/intel/isl/isl.c | 9 +++++++--
src/intel/isl/isl.h | 12 ++++++++++--
src/intel/isl/isl_drm.c | 2 ++
src/intel/isl/isl_gen7.c | 8 +++++++-
src/intel/isl/isl_surface_state.c | 2 ++
5 files changed, 28 insertions(+), 5 deletions(-)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 392c15ca3fb..3ffc6f627b2 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -218,8 +218,11 @@ isl_tiling_get_info(enum isl_tiling tiling,
break;
case ISL_TILING_GEN9_Yf:
- case ISL_TILING_GEN9_Ys: {
- bool is_Ys = tiling == ISL_TILING_GEN9_Ys;
+ case ISL_TILING_GEN9_Ys:
+ case ISL_TILING_GEN10_Yf:
+ case ISL_TILING_GEN10_Ys: {
+ bool is_Ys = tiling == ISL_TILING_GEN9_Ys ||
+ tiling == ISL_TILING_GEN10_Ys;
assert(bs > 0);
unsigned width = 1 << (6 + (ffs(bs) / 2) + (2 * is_Ys));
@@ -375,7 +378,9 @@ isl_surf_choose_tiling(const struct isl_device *dev,
CHOOSE(ISL_TILING_LINEAR);
}
+ CHOOSE(ISL_TILING_GEN10_Ys);
CHOOSE(ISL_TILING_GEN9_Ys);
+ CHOOSE(ISL_TILING_GEN10_Yf);
CHOOSE(ISL_TILING_GEN9_Yf);
CHOOSE(ISL_TILING_Y0);
CHOOSE(ISL_TILING_X);
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 1c7990f2dc7..200bfbfa85b 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -462,6 +462,8 @@ enum isl_tiling {
ISL_TILING_Y0, /**< Legacy Y tiling */
ISL_TILING_GEN9_Yf, /**< Standard 4K tiling. The 'f' means "four". */
ISL_TILING_GEN9_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
+ ISL_TILING_GEN10_Yf, /**< Standard 4K tiling. The 'f' means "four". */
+ ISL_TILING_GEN10_Ys, /**< Standard 64K tiling. The 's' means "sixty-four".
*/
ISL_TILING_HIZ, /**< Tiling format for HiZ surfaces */
ISL_TILING_CCS, /**< Tiling format for CCS surfaces */
};
@@ -477,6 +479,8 @@ typedef uint32_t isl_tiling_flags_t;
#define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
#define ISL_TILING_GEN9_Yf_BIT (1u << ISL_TILING_GEN9_Yf)
#define ISL_TILING_GEN9_Ys_BIT (1u << ISL_TILING_GEN9_Ys)
+#define ISL_TILING_GEN10_Yf_BIT (1u << ISL_TILING_GEN10_Yf)
+#define ISL_TILING_GEN10_Ys_BIT (1u << ISL_TILING_GEN10_Ys)
#define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ)
#define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS)
#define ISL_TILING_ANY_MASK (~0u)
@@ -485,11 +489,15 @@ typedef uint32_t isl_tiling_flags_t;
/** Any Y tiling, including legacy Y tiling. */
#define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
ISL_TILING_GEN9_Yf_BIT | \
- ISL_TILING_GEN9_Ys_BIT)
+ ISL_TILING_GEN9_Ys_BIT | \
+ ISL_TILING_GEN10_Yf_BIT | \
+ ISL_TILING_GEN10_Ys_BIT)
/** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
#define ISL_TILING_STD_Y_MASK (ISL_TILING_GEN9_Yf_BIT | \
- ISL_TILING_GEN9_Ys_BIT)
+ ISL_TILING_GEN9_Ys_BIT | \
+ ISL_TILING_GEN10_Yf_BIT | \
+ ISL_TILING_GEN10_Ys_BIT)
/** @} */
/**
diff --git a/src/intel/isl/isl_drm.c b/src/intel/isl/isl_drm.c
index 62fdd22d10d..03f433a1058 100644
--- a/src/intel/isl/isl_drm.c
+++ b/src/intel/isl/isl_drm.c
@@ -46,6 +46,8 @@ isl_tiling_to_i915_tiling(enum isl_tiling tiling)
case ISL_TILING_W:
case ISL_TILING_GEN9_Yf:
case ISL_TILING_GEN9_Ys:
+ case ISL_TILING_GEN10_Yf:
+ case ISL_TILING_GEN10_Ys:
case ISL_TILING_HIZ:
case ISL_TILING_CCS:
return I915_TILING_NONE;
diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c
index 91cea299abc..f6f7e1ba7dc 100644
--- a/src/intel/isl/isl_gen7.c
+++ b/src/intel/isl/isl_gen7.c
@@ -197,16 +197,22 @@ isl_gen6_filter_tiling(const struct isl_device *dev,
assert(ISL_DEV_USE_SEPARATE_STENCIL(dev));
/* Clear flags unsupported on this hardware */
- if (ISL_DEV_GEN(dev) < 9) {
+ if (ISL_DEV_GEN(dev) != 9) {
*flags &= ~ISL_TILING_GEN9_Yf_BIT;
*flags &= ~ISL_TILING_GEN9_Ys_BIT;
}
+ if (ISL_DEV_GEN(dev) < 10) {
+ *flags &= ~ISL_TILING_GEN10_Yf_BIT;
+ *flags &= ~ISL_TILING_GEN10_Ys_BIT;
+ }
/* And... clear the Yf and Ys bits anyway because Anvil doesn't support
* them yet.
*/
*flags &= ~ISL_TILING_GEN9_Yf_BIT; /* FINISHME[SKL]: Support Yf */
*flags &= ~ISL_TILING_GEN9_Ys_BIT; /* FINISHME[SKL]: Support Ys */
+ *flags &= ~ISL_TILING_GEN10_Yf_BIT; /* FINISHME[SKL]: Support Yf */
+ *flags &= ~ISL_TILING_GEN10_Ys_BIT; /* FINISHME[SKL]: Support Ys */
if (isl_surf_usage_is_depth(info->usage)) {
/* Depth requires Y. */
diff --git a/src/intel/isl/isl_surface_state.c
b/src/intel/isl/isl_surface_state.c
index 6ac0969f00c..26cb2a87c55 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -72,6 +72,8 @@ static const uint8_t isl_to_gen_tiling[] = {
[ISL_TILING_Y0] = YMAJOR,
[ISL_TILING_GEN9_Yf] = YMAJOR,
[ISL_TILING_GEN9_Ys] = YMAJOR,
+ [ISL_TILING_GEN10_Yf] = YMAJOR,
+ [ISL_TILING_GEN10_Ys] = YMAJOR,
[ISL_TILING_W] = WMAJOR,
};
#endif
--
2.19.1
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