Tested-by: Jakob Bornecrantz <ja...@collabora.com>
On Wed, Oct 17, 2018 at 5:29 PM Marek Olšák <mar...@gmail.com> wrote:
>
> From: Marek Olšák <marek.ol...@amd.com>
>
> This fixes dEQP-GLES2.functional.rasterization.limits.points.
> Broken by: ea039f789d9b54e1bd1d644b6a29863ca3500314
> ---
> src/gallium/drivers/radeonsi/si_get.c | 5 +++--
> src/gallium/drivers/radeonsi/si_pipe.h | 1 +
> src/gallium/drivers/radeonsi/si_state.c | 2 +-
> 3 files changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_get.c
> b/src/gallium/drivers/radeonsi/si_get.c
> index ac302b8a946..804276b3eda 100644
> --- a/src/gallium/drivers/radeonsi/si_get.c
> +++ b/src/gallium/drivers/radeonsi/si_get.c
> @@ -326,25 +326,26 @@ static int si_get_param(struct pipe_screen *pscreen,
> enum pipe_cap param)
> default:
> return u_pipe_screen_get_param_defaults(pscreen, param);
> }
> }
>
> static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
> {
> switch (param) {
> case PIPE_CAPF_MAX_LINE_WIDTH:
> case PIPE_CAPF_MAX_LINE_WIDTH_AA:
> - case PIPE_CAPF_MAX_POINT_WIDTH:
> - case PIPE_CAPF_MAX_POINT_WIDTH_AA:
> /* This depends on the quant mode, though the precise
> interactions
> * are unknown. */
> return 2048;
> + case PIPE_CAPF_MAX_POINT_WIDTH:
> + case PIPE_CAPF_MAX_POINT_WIDTH_AA:
> + return SI_MAX_POINT_SIZE;
> case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
> return 16.0f;
> case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
> return 16.0f;
> case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
> case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
> case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
> return 0.0f;
> }
> return 0.0f;
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
> b/src/gallium/drivers/radeonsi/si_pipe.h
> index 6edc06cece7..dc95afb7421 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.h
> +++ b/src/gallium/drivers/radeonsi/si_pipe.h
> @@ -41,20 +41,21 @@
> #define ATI_VENDOR_ID 0x1002
>
> #define SI_NOT_QUERY 0xffffffff
>
> /* The base vertex and primitive restart can be any number, but we must pick
> * one which will mean "unknown" for the purpose of state tracking and
> * the number shouldn't be a commonly-used one. */
> #define SI_BASE_VERTEX_UNKNOWN INT_MIN
> #define SI_RESTART_INDEX_UNKNOWN INT_MIN
> #define SI_NUM_SMOOTH_AA_SAMPLES 8
> +#define SI_MAX_POINT_SIZE 2048
> #define SI_GS_PER_ES 128
> /* Alignment for optimal CP DMA performance. */
> #define SI_CPDMA_ALIGNMENT 32
>
> /* Tunables for compute-based clear_buffer and copy_buffer: */
> #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
> #define SI_COMPUTE_COPY_DW_PER_THREAD 4
> #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
>
> /* Pipeline & streamout query controls. */
> diff --git a/src/gallium/drivers/radeonsi/si_state.c
> b/src/gallium/drivers/radeonsi/si_state.c
> index 8b2e6e57f45..176ec749148 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -891,21 +891,21 @@ static void *si_create_rs_state(struct pipe_context
> *ctx,
> S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
> S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
> S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode !=
> PIPE_SPRITE_COORD_UPPER_LEFT));
>
> /* point size 12.4 fixed point */
> tmp = (unsigned)(state->point_size * 8.0);
> si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) |
> S_028A00_WIDTH(tmp));
>
> if (state->point_size_per_vertex) {
> psize_min = util_get_min_point_size(state);
> - psize_max = 8192;
> + psize_max = SI_MAX_POINT_SIZE;
> } else {
> /* Force the point size to be as if the vertex output was
> disabled. */
> psize_min = state->point_size;
> psize_max = state->point_size;
> }
> rs->max_point_size = psize_max;
>
> /* Divide by two, because 0.5 = 1 pixel. */
> si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
> S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
> --
> 2.17.1
>
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