Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
On 25/10/2018 18:14, Anuj Phogat wrote:
The default setting of this bit is not the desirable behavior.
WA_1406697149
Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
src/intel/genxml/gen11.xml | 1 +
src/intel/vulkan/genX_cmd_buffer.c | 7 +++++++
2 files changed, 8 insertions(+)
diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index c69d7dc89c2..454ef8f4103 100644
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -3546,6 +3546,7 @@
<register name="L3CNTLREG" length="1" num="0x7034">
<field name="SLM Enable" start="0" end="0" type="uint"/>
<field name="URB Allocation" start="1" end="7" type="uint"/>
+ <field name="Error Detection Behavior Control" start="9" end="9"
type="bool"/>
<field name="RO Allocation" start="11" end="17" type="uint"/>
<field name="DC Allocation" start="18" end="24" type="uint"/>
<field name="All Allocation" start="25" end="31" type="uint"/>
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index 43a02f22567..ed88157170d 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -1617,6 +1617,13 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer
*cmd_buffer,
uint32_t l3cr;
anv_pack_struct(&l3cr, GENX(L3CNTLREG),
.SLMEnable = has_slm,
+#if GEN_GEN == 11
+ /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
+ * in L3CNTLREG register. The default setting of the bit is not the
+ * desirable behavior.
+ */
+ .ErrorDetectionBehaviorControl = true,
+#endif
.URBAllocation = cfg->n[GEN_L3P_URB],
.ROAllocation = cfg->n[GEN_L3P_RO],
.DCAllocation = cfg->n[GEN_L3P_DC],
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