On Sun, Oct 28, 2018 at 2:42 AM Timothy Arceri <[email protected]> wrote: > > On 28/10/18 12:18 pm, Jason Ekstrand wrote: > > On Sat, Oct 27, 2018 at 8:03 PM Timothy Arceri <[email protected] > > <mailto:[email protected]>> wrote: > > > > From: Timothy Arceri <[email protected]> > > > > Commit 8d8222461f9d7f49 caused substantially more URB messages in > > geometry and tessellation shaders (due to enabling > > nir_lower_io_to_scalar_early). This combines io again to avoid > > this regression while still allowing link time optimisation of > > components. > > > > Shader-db results (SKL): > > > > total instructions in shared programs: 13107449 -> 13104666 (-0.02%) > > instructions in affected programs: 304803 -> 302020 (-0.91%) > > helped: 1136 > > HURT: 409 > > > > total cycles in shared programs: 332066434 -> 332125306 (0.02%) > > cycles in affected programs: 70735188 -> 70794060 (0.08%) > > helped: 11797 > > HURT: 13257 > > > > LOST: 2 > > GAINED: 1 > > > > Most of the cycle/instruction changes is with fragment shaders. > > > > > > Why are we running it on fragment shaders? > > The pass was originally written for radv/radeonsi and as far as I can > tell this is what LLVM does for those drivers.
Wait what? GCN only has scalar input instructions for fragment shaders so there is no vectorization going on. > > > They don't benefit at all > > from vector I/O. For that matter, why does it affect them at all? > > Just a guess from what I have seen in radv but it's probably a scheduler > thing. e.g We do the (vec4) load at the start of the shader in some > cases one of the components might not be used until much later. In RADV > this was adding to VGPR register pressure. > > > > > --Jason > > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107510 > > --- > > src/intel/vulkan/anv_pipeline.c | 6 ++++++ > > src/mesa/drivers/dri/i965/brw_link.cpp | 6 ++++++ > > 2 files changed, 12 insertions(+) > > > > diff --git a/src/intel/vulkan/anv_pipeline.c > > b/src/intel/vulkan/anv_pipeline.c > > index 7c9b1230115..63acb3cc25e 100644 > > --- a/src/intel/vulkan/anv_pipeline.c > > +++ b/src/intel/vulkan/anv_pipeline.c > > @@ -1016,6 +1016,12 @@ anv_pipeline_compile_graphics(struct > > anv_pipeline *pipeline, > > > > void *stage_ctx = ralloc_context(NULL); > > > > + if (nir_opt_vectorize_io(stages[s].nir)) { > > + brw_nir_optimize(stages[s].nir, compiler, > > + > > compiler->scalar_stage[stages[s].nir->info.stage], > > + false); > > + } > > + > > anv_pipeline_lower_nir(pipeline, stage_ctx, &stages[s], layout); > > > > const unsigned *code; > > diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp > > b/src/mesa/drivers/dri/i965/brw_link.cpp > > index 2cbb1e0b879..0bcd73af04c 100644 > > --- a/src/mesa/drivers/dri/i965/brw_link.cpp > > +++ b/src/mesa/drivers/dri/i965/brw_link.cpp > > @@ -319,6 +319,12 @@ brw_link_shader(struct gl_context *ctx, struct > > gl_shader_program *shProg) > > > > struct gl_program *prog = shader->Program; > > > > + if (nir_opt_vectorize_io(prog->nir)) { > > + brw_nir_optimize(prog->nir, compiler, > > + compiler->scalar_stage[prog->info.stage], > > + false); > > + } > > + > > _mesa_update_shader_textures_used(shProg, prog); > > > > brw_shader_gather_info(prog->nir, prog); > > -- > > 2.17.2 > > > > _______________________________________________ > > mesa-dev mailing list > > [email protected] <mailto:[email protected]> > > https://lists.freedesktop.org/mailman/listinfo/mesa-dev > > > _______________________________________________ > mesa-dev mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/mesa-dev _______________________________________________ mesa-dev mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-dev
