Reviewed-by: Ilia Mirkin <imir...@alum.mit.edu>
I suspect this was to take advantage of the 32-bit addressing modes available on Fermi. No code was ever written for this though (or if it was, it's now long-deleted). On Mon, Oct 29, 2018 at 1:16 PM Eric Engestrom <eric.engest...@intel.com> wrote: > > Signed-off-by: Eric Engestrom <eric.engest...@intel.com> > --- > src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h > b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h > index 4136b1ecfebcd7d7d1a5..e0f50ab0904289646c7c 100644 > --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h > +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h > @@ -184,7 +184,6 @@ class NVC0LoweringPass : public Pass > private: > const Target *const targ; > > - Symbol *gMemBase; > LValue *gpEmitAddress; > }; > > -- > Cheers, > Eric > > _______________________________________________ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
