From: Marek Olšák <[email protected]>
and add has_dcc_constant_encode.
---
src/gallium/drivers/radeonsi/si_clear.c | 10 ++++++++--
src/gallium/drivers/radeonsi/si_pipe.c | 1 +
src/gallium/drivers/radeonsi/si_pipe.h | 1 +
src/gallium/drivers/radeonsi/si_state.c | 2 +-
4 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_clear.c
b/src/gallium/drivers/radeonsi/si_clear.c
index 2900c31fd21..b13eecb9ec5 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -205,22 +205,22 @@ static bool vi_get_fast_clear_parameters(enum pipe_format
base_format,
/* Check if all color values are equal if they are present. */
for (int i = 0; i < 4; ++i) {
if (desc->swizzle[i] <= PIPE_SWIZZLE_W &&
desc->swizzle[i] != alpha_channel &&
values[i] != color_value)
return true; /* require ELIMINATE_FAST_CLEAR */
}
/* This doesn't need ELIMINATE_FAST_CLEAR.
- * CB uses both the DCC clear codes and the CB clear color registers,
- * so they must match.
+ * On chips predating Raven2, the DCC clear codes and the CB clear
+ * color registers must match.
*/
*eliminate_needed = false;
if (color_value) {
if (alpha_value)
*clear_value = DCC_CLEAR_COLOR_1111;
else
*clear_value = DCC_CLEAR_COLOR_1110;
} else {
if (alpha_value)
@@ -541,20 +541,26 @@ static void si_do_fast_color_clear(struct si_context
*sctx,
!(tex->dirty_level_mask & (1 << level))) {
tex->dirty_level_mask |= 1 << level;
p_atomic_inc(&sctx->screen->compressed_colortex_counter);
}
/* We can change the micro tile mode before a full clear. */
si_set_optimal_micro_tile_mode(sctx->screen, tex);
*buffers &= ~clear_bit;
+ /* Chips with DCC constant encoding don't need to set the clear
+ * color registers for DCC clear values 0 and 1.
+ */
+ if (sctx->screen->has_dcc_constant_encode && !eliminate_needed)
+ continue;
+
if (si_set_clear_color(tex, fb->cbufs[i]->format, color)) {
sctx->framebuffer.dirty_cbufs |= 1 << i;
si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
}
}
}
static void si_clear(struct pipe_context *ctx, unsigned buffers,
const union pipe_color_union *color,
double depth, unsigned stencil)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index 490a3714836..ba406bee922 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1022,20 +1022,21 @@ struct pipe_screen *radeonsi_screen_create(struct
radeon_winsys *ws,
sscreen->commutative_blend_add =
driQueryOptionb(config->options,
"radeonsi_commutative_blend_add");
sscreen->clear_db_cache_before_clear =
driQueryOptionb(config->options,
"radeonsi_clear_db_cache_before_clear");
sscreen->has_msaa_sample_loc_bug = (sscreen->info.family >=
CHIP_POLARIS10 &&
sscreen->info.family <=
CHIP_POLARIS12) ||
sscreen->info.family == CHIP_VEGA10
||
sscreen->info.family == CHIP_RAVEN;
sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 ||
sscreen->info.family == CHIP_RAVEN;
+ sscreen->has_dcc_constant_encode = sscreen->info.family == CHIP_RAVEN2;
if (sscreen->debug_flags & DBG(DPBB)) {
sscreen->dpbb_allowed = true;
} else {
/* Only enable primitive binning on APUs by default. */
/* TODO: Investigate if binning is profitable on Vega12. */
sscreen->dpbb_allowed = !(sscreen->debug_flags & DBG(NO_DPBB))
&&
(sscreen->info.family == CHIP_RAVEN ||
sscreen->info.family == CHIP_RAVEN2);
}
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index 0807c8ddacc..023e0f0a0f9 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -438,20 +438,21 @@ struct si_screen {
unsigned eqaa_force_color_samples;
bool has_clear_state;
bool has_distributed_tess;
bool has_draw_indirect_multi;
bool has_out_of_order_rast;
bool assume_no_z_fights;
bool commutative_blend_add;
bool clear_db_cache_before_clear;
bool has_msaa_sample_loc_bug;
bool has_ls_vgpr_init_bug;
+ bool has_dcc_constant_encode;
bool dpbb_allowed;
bool dfsm_allowed;
bool llvm_has_working_vgpr_indexing;
/* Whether shaders are monolithic (1-part) or separate (3-part). */
bool use_monolithic_shaders;
bool record_llvm_ir;
bool has_rbplus; /* if RB+ registers
exist */
bool rbplus_allowed; /* if RB+ is allowed */
bool dcc_msaa_allowed;
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 0293bdfa791..e3b45fa6ea7 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -114,21 +114,21 @@ static void si_emit_cb_render_state(struct si_context
*sctx)
blend->blend_enable_4bit & cb_target_mask &&
sctx->framebuffer.nr_samples >= 2;
unsigned watermark =
sctx->framebuffer.dcc_overwrite_combiner_watermark;
radeon_opt_set_context_reg(
sctx, R_028424_CB_DCC_CONTROL,
SI_TRACKED_CB_DCC_CONTROL,
S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable)
|
-
S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->family == CHIP_RAVEN2));
+
S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->screen->has_dcc_constant_encode));
}
/* RB+ register settings. */
if (sctx->screen->rbplus_allowed) {
unsigned spi_shader_col_format =
sctx->ps_shader.cso ?
sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
unsigned sx_ps_downconvert = 0;
unsigned sx_blend_opt_epsilon = 0;
unsigned sx_blend_opt_control = 0;
--
2.17.1
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