Ported from RadeonSI.
Signed-off-by: Samuel Pitoiset <[email protected]>
---
src/amd/vulkan/radv_cmd_buffer.c | 7 +++++++
src/amd/vulkan/radv_device.c | 12 ++++++++++++
src/amd/vulkan/radv_private.h | 2 ++
src/amd/vulkan/si_cmd_buffer.c | 3 ---
4 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index ee5373950f..a5788d6ad3 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1541,6 +1541,13 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer)
S_028208_BR_X(framebuffer->width) |
S_028208_BR_Y(framebuffer->height));
+ if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
+ uint8_t watermark =
framebuffer->dcc_overwrite_combiner_watermark;
+ radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
+
S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
+
S_028424_OVERWRITE_COMBINER_WATERMARK(watermark));
+ }
+
if (cmd_buffer->device->dfsm_allowed) {
radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) |
EVENT_INDEX(0));
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 92254bed2e..2b88970986 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -4373,6 +4373,7 @@ VkResult radv_CreateFramebuffer(
{
RADV_FROM_HANDLE(radv_device, device, _device);
struct radv_framebuffer *framebuffer;
+ unsigned num_bpp64_colorbufs = 0;
assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
@@ -4393,6 +4394,9 @@ VkResult radv_CreateFramebuffer(
framebuffer->attachments[i].attachment = iview;
if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
radv_initialise_color_surface(device,
&framebuffer->attachments[i].cb, iview);
+
+ if (iview->image->surface.bpe >= 8)
+ num_bpp64_colorbufs++;
} else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT |
VK_IMAGE_ASPECT_STENCIL_BIT)) {
radv_initialise_ds_surface(device,
&framebuffer->attachments[i].ds, iview);
}
@@ -4401,6 +4405,14 @@ VkResult radv_CreateFramebuffer(
framebuffer->layers = MIN2(framebuffer->layers,
radv_surface_max_layer_count(iview));
}
+ /* For optimal DCC performance. */
+ if (device->physical_device->rad_info.chip_class == VI)
+ framebuffer->dcc_overwrite_combiner_watermark = 4;
+ else if (num_bpp64_colorbufs >= 5)
+ framebuffer->dcc_overwrite_combiner_watermark = 8;
+ else
+ framebuffer->dcc_overwrite_combiner_watermark = 6;
+
*pFramebuffer = radv_framebuffer_to_handle(framebuffer);
return VK_SUCCESS;
}
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 1628be1002..dc7372df76 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1772,6 +1772,8 @@ struct radv_framebuffer {
uint32_t height;
uint32_t layers;
+ uint8_t dcc_overwrite_combiner_watermark;
+
uint32_t attachment_count;
struct radv_attachment_info attachments[0];
};
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index be37191306..7a0f4e914d 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -306,9 +306,6 @@ si_emit_graphics(struct radv_physical_device
*physical_device,
if (physical_device->rad_info.chip_class >= VI) {
uint32_t vgt_tess_distribution;
- radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
-
S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
-
S_028424_OVERWRITE_COMBINER_WATERMARK(4));
vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
S_028B50_ACCUM_TRI(11) |
--
2.19.1
_______________________________________________
mesa-dev mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
