We don't need to flush anything before these two commands as well.
This is because they have to be externally synchronized, so the
app should have called CmdPipelineBarrier() prior to that and the
driver should have flushed the caches.
Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
---
src/amd/vulkan/radv_meta_clear.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index e82b6fd2f58..db62fdf65f9 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -954,9 +954,7 @@ emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) & ~ *pre_flush;
*pre_flush |= cmd_buffer->state.flush_bits;
- } else
- cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
-
RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
+ }
if (htile_mask == UINT_MAX) {
/* Clear the whole HTILE buffer. */
@@ -1410,9 +1408,7 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) & ~ *pre_flush;
*pre_flush |= cmd_buffer->state.flush_bits;
- } else
- cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
-
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
+ }
cmask_clear_value = radv_get_cmask_fast_clear_value(iview->image);
--
2.19.1
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