From: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reduce the number of places that encode buffer descriptors.
---
.../drivers/radeonsi/si_state_streamout.c | 61 ++++---------------
1 file changed, 11 insertions(+), 50 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_streamout.c
b/src/gallium/drivers/radeonsi/si_state_streamout.c
index fd7e843bc48..83ca23a8bf2 100644
--- a/src/gallium/drivers/radeonsi/si_state_streamout.c
+++ b/src/gallium/drivers/radeonsi/si_state_streamout.c
@@ -86,24 +86,22 @@ void si_streamout_buffers_dirty(struct si_context *sctx)
si_mark_atom_dirty(sctx, &sctx->atoms.s.streamout_begin);
si_set_streamout_enable(sctx, true);
}
static void si_set_streamout_targets(struct pipe_context *ctx,
unsigned num_targets,
struct pipe_stream_output_target **targets,
const unsigned *offsets)
{
struct si_context *sctx = (struct si_context *)ctx;
- struct si_buffer_resources *buffers = &sctx->rw_buffers;
- struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
unsigned old_num_targets = sctx->streamout.num_targets;
- unsigned i, bufidx;
+ unsigned i;
/* We are going to unbind the buffers. Mark which caches need to be
flushed. */
if (sctx->streamout.num_targets && sctx->streamout.begin_emitted) {
/* Since streamout uses vector writes which go through TC L2
* and most other clients can use TC L2 as well, we don't need
* to flush it.
*
* The only cases which requires flushing it is VGT DMA index
* fetching (on <= CIK) and indirect draw data, which are rare
* cases. Thus, flag the TC L2 dirtiness in the resource and
@@ -168,71 +166,34 @@ static void si_set_streamout_targets(struct pipe_context
*ctx,
/* Update dirty state bits. */
if (num_targets) {
si_streamout_buffers_dirty(sctx);
} else {
si_set_atom_dirty(sctx, &sctx->atoms.s.streamout_begin, false);
si_set_streamout_enable(sctx, false);
}
/* Set the shader resources.*/
for (i = 0; i < num_targets; i++) {
- bufidx = SI_VS_STREAMOUT_BUF0 + i;
-
if (targets[i]) {
- struct pipe_resource *buffer = targets[i]->buffer;
- uint64_t va = r600_resource(buffer)->gpu_address;
-
- /* Set the descriptor.
- *
- * On VI, the format must be non-INVALID, otherwise
- * the buffer will be considered not bound and store
- * instructions will be no-ops.
- */
- uint32_t *desc = descs->list + bufidx*4;
- desc[0] = va;
- desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
- desc[2] = 0xffffffff;
- desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
- S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
- S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
- S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
-
S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
-
- /* Set the resource. */
- pipe_resource_reference(&buffers->buffers[bufidx],
- buffer);
- radeon_add_to_gfx_buffer_list_check_mem(sctx,
-
r600_resource(buffer),
-
buffers->shader_usage,
-
RADEON_PRIO_SHADER_RW_BUFFER,
- true);
- r600_resource(buffer)->bind_history |=
PIPE_BIND_STREAM_OUTPUT;
-
- buffers->enabled_mask |= 1u << bufidx;
+ struct pipe_shader_buffer sbuf;
+ sbuf.buffer = targets[i]->buffer;
+ sbuf.buffer_offset = 0;
+ sbuf.buffer_size = targets[i]->buffer_offset +
+ targets[i]->buffer_size;
+ si_set_rw_shader_buffer(sctx, SI_VS_STREAMOUT_BUF0 + i,
&sbuf);
+ r600_resource(targets[i]->buffer)->bind_history |=
PIPE_BIND_STREAM_OUTPUT;
} else {
- /* Clear the descriptor and unset the resource. */
- memset(descs->list + bufidx*4, 0,
- sizeof(uint32_t) * 4);
- pipe_resource_reference(&buffers->buffers[bufidx],
- NULL);
- buffers->enabled_mask &= ~(1u << bufidx);
+ si_set_rw_shader_buffer(sctx, SI_VS_STREAMOUT_BUF0 + i,
NULL);
}
}
- for (; i < old_num_targets; i++) {
- bufidx = SI_VS_STREAMOUT_BUF0 + i;
- /* Clear the descriptor and unset the resource. */
- memset(descs->list + bufidx*4, 0, sizeof(uint32_t) * 4);
- pipe_resource_reference(&buffers->buffers[bufidx], NULL);
- buffers->enabled_mask &= ~(1u << bufidx);
- }
-
- sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
+ for (; i < old_num_targets; i++)
+ si_set_rw_shader_buffer(sctx, SI_VS_STREAMOUT_BUF0 + i, NULL);
}
static void si_flush_vgt_streamout(struct si_context *sctx)
{
struct radeon_cmdbuf *cs = sctx->gfx_cs;
unsigned reg_strmout_cntl;
/* The register is at different places on different ASICs. */
if (sctx->chip_class >= CIK) {
reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
--
2.19.1
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