Generated with a little hand-editing and the following sed commands: sed -i 's/nir_op_ball_fequal/nir_op_b32all_fequal/g' **/*.c sed -i 's/nir_op_bany_fnequal/nir_op_b32any_fnequal/g' **/*.c sed -i 's/nir_op_ball_iequal/nir_op_b32all_iequal/g' **/*.c sed -i 's/nir_op_bany_inequal/nir_op_b32any_inequal/g' **/*.c sed -i 's/nir_op_\([fiu]lt\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fiu]ge\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fiu]ne\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fiu]eq\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fi]\)ne32g/nir_op_\1neg/g' **/*.c sed -i 's/nir_op_bcsel/nir_op_b32csel/g' **/*.c --- src/amd/common/ac_nir_to_llvm.c | 22 ++-- src/broadcom/compiler/nir_to_vir.c | 44 +++---- src/freedreno/ir3/ir3_compiler_nir.c | 22 ++-- src/gallium/auxiliary/nir/tgsi_to_nir.c | 20 +-- src/gallium/drivers/vc4/vc4_program.c | 40 +++--- src/intel/compiler/brw_fs_nir.cpp | 66 +++++----- .../brw_nir_analyze_boolean_resolves.c | 24 ++-- src/intel/compiler/brw_vec4_nir.cpp | 114 +++++++++--------- 8 files changed, 176 insertions(+), 176 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index fe65dfff8f3..92182bb5be5 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@ -687,34 +687,34 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr) LLVMTypeOf(src[0]), ""), ""); break; - case nir_op_ilt: + case nir_op_ilt32: result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]); break; - case nir_op_ine: + case nir_op_ine32: result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]); break; - case nir_op_ieq: + case nir_op_ieq32: result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]); break; - case nir_op_ige: + case nir_op_ige32: result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]); break; - case nir_op_ult: + case nir_op_ult32: result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]); break; - case nir_op_uge: + case nir_op_uge32: result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]); break; - case nir_op_feq: + case nir_op_feq32: result = emit_float_cmp(&ctx->ac, LLVMRealOEQ, src[0], src[1]); break; - case nir_op_fne: + case nir_op_fne32: result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]); break; - case nir_op_flt: + case nir_op_flt32: result = emit_float_cmp(&ctx->ac, LLVMRealOLT, src[0], src[1]); break; - case nir_op_fge: + case nir_op_fge32: result = emit_float_cmp(&ctx->ac, LLVMRealOGE, src[0], src[1]); break; case nir_op_fabs: @@ -916,7 +916,7 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr) else result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, ""); break; - case nir_op_bcsel: + case nir_op_b32csel: result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]); break; case nir_op_find_lsb: diff --git a/src/broadcom/compiler/nir_to_vir.c b/src/broadcom/compiler/nir_to_vir.c index fbe8af376a7..37c83326d23 100644 --- a/src/broadcom/compiler/nir_to_vir.c +++ b/src/broadcom/compiler/nir_to_vir.c @@ -506,45 +506,45 @@ ntq_emit_comparison(struct v3d_compile *c, struct qreg *dest, bool cond_invert = false; switch (compare_instr->op) { - case nir_op_feq: + case nir_op_feq32: case nir_op_seq: vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ); break; - case nir_op_ieq: + case nir_op_ieq32: vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ); break; - case nir_op_fne: + case nir_op_fne32: case nir_op_sne: vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ); cond_invert = true; break; - case nir_op_ine: + case nir_op_ine32: vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ); cond_invert = true; break; - case nir_op_fge: + case nir_op_fge32: case nir_op_sge: vir_PF(c, vir_FCMP(c, src1, src0), V3D_QPU_PF_PUSHC); break; - case nir_op_ige: + case nir_op_ige32: vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC); cond_invert = true; break; - case nir_op_uge: + case nir_op_uge32: vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC); cond_invert = true; break; case nir_op_slt: - case nir_op_flt: + case nir_op_flt32: vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHN); break; - case nir_op_ilt: + case nir_op_ilt32: vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC); break; - case nir_op_ult: + case nir_op_ult32: vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC); break; @@ -565,7 +565,7 @@ ntq_emit_comparison(struct v3d_compile *c, struct qreg *dest, vir_uniform_f(c, 1.0), vir_uniform_f(c, 0.0)); break; - case nir_op_bcsel: + case nir_op_b32csel: *dest = vir_SEL(c, cond, ntq_get_alu_src(c, sel_instr, 1), ntq_get_alu_src(c, sel_instr, 2)); @@ -748,22 +748,22 @@ ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr) case nir_op_sne: case nir_op_sge: case nir_op_slt: - case nir_op_feq: - case nir_op_fne: - case nir_op_fge: - case nir_op_flt: - case nir_op_ieq: - case nir_op_ine: - case nir_op_ige: - case nir_op_uge: - case nir_op_ilt: - case nir_op_ult: + case nir_op_feq32: + case nir_op_fne32: + case nir_op_fge32: + case nir_op_flt32: + case nir_op_ieq32: + case nir_op_ine32: + case nir_op_ige32: + case nir_op_uge32: + case nir_op_ilt32: + case nir_op_ult32: if (!ntq_emit_comparison(c, &result, instr, instr)) { fprintf(stderr, "Bad comparison instruction\n"); } break; - case nir_op_bcsel: + case nir_op_b32csel: result = ntq_emit_bcsel(c, instr, src); break; case nir_op_fcsel: diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c index 3e974531a9e..0c09db0c295 100644 --- a/src/freedreno/ir3/ir3_compiler_nir.c +++ b/src/freedreno/ir3/ir3_compiler_nir.c @@ -1182,22 +1182,22 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu) dst[0]->cat5.type = TYPE_F32; break; break; - case nir_op_flt: + case nir_op_flt32: dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_LT; dst[0] = ir3_n2b(b, dst[0]); break; - case nir_op_fge: + case nir_op_fge32: dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_GE; dst[0] = ir3_n2b(b, dst[0]); break; - case nir_op_feq: + case nir_op_feq32: dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_EQ; dst[0] = ir3_n2b(b, dst[0]); break; - case nir_op_fne: + case nir_op_fne32: dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_NE; dst[0] = ir3_n2b(b, dst[0]); @@ -1310,38 +1310,38 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu) case nir_op_ushr: dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0); break; - case nir_op_ilt: + case nir_op_ilt32: dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_LT; dst[0] = ir3_n2b(b, dst[0]); break; - case nir_op_ige: + case nir_op_ige32: dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_GE; dst[0] = ir3_n2b(b, dst[0]); break; - case nir_op_ieq: + case nir_op_ieq32: dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_EQ; dst[0] = ir3_n2b(b, dst[0]); break; - case nir_op_ine: + case nir_op_ine32: dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_NE; dst[0] = ir3_n2b(b, dst[0]); break; - case nir_op_ult: + case nir_op_ult32: dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_LT; dst[0] = ir3_n2b(b, dst[0]); break; - case nir_op_uge: + case nir_op_uge32: dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_GE; dst[0] = ir3_n2b(b, dst[0]); break; - case nir_op_bcsel: { + case nir_op_b32csel: { struct ir3_instruction *cond = ir3_b2n(b, src[0]); compile_assert(ctx, bs[1] == bs[2]); /* the boolean condition is 32b even if src[1] and src[2] are diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c b/src/gallium/auxiliary/nir/tgsi_to_nir.c index 0ad274b535a..6627681d928 100644 --- a/src/gallium/auxiliary/nir/tgsi_to_nir.c +++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c @@ -1471,10 +1471,10 @@ static const nir_op op_trans[TGSI_OPCODE_LAST] = { [TGSI_OPCODE_ENDSUB] = 0, /* XXX: no function calls */ [TGSI_OPCODE_NOP] = 0, - [TGSI_OPCODE_FSEQ] = nir_op_feq, - [TGSI_OPCODE_FSGE] = nir_op_fge, - [TGSI_OPCODE_FSLT] = nir_op_flt, - [TGSI_OPCODE_FSNE] = nir_op_fne, + [TGSI_OPCODE_FSEQ] = nir_op_feq32, + [TGSI_OPCODE_FSGE] = nir_op_fge32, + [TGSI_OPCODE_FSLT] = nir_op_flt32, + [TGSI_OPCODE_FSNE] = nir_op_fne32, [TGSI_OPCODE_KILL_IF] = 0, @@ -1485,9 +1485,9 @@ static const nir_op op_trans[TGSI_OPCODE_LAST] = { [TGSI_OPCODE_IMAX] = nir_op_imax, [TGSI_OPCODE_IMIN] = nir_op_imin, [TGSI_OPCODE_INEG] = nir_op_ineg, - [TGSI_OPCODE_ISGE] = nir_op_ige, + [TGSI_OPCODE_ISGE] = nir_op_ige32, [TGSI_OPCODE_ISHR] = nir_op_ishr, - [TGSI_OPCODE_ISLT] = nir_op_ilt, + [TGSI_OPCODE_ISLT] = nir_op_ilt32, [TGSI_OPCODE_F2U] = nir_op_f2u32, [TGSI_OPCODE_U2F] = nir_op_u2f32, [TGSI_OPCODE_UADD] = nir_op_iadd, @@ -1497,11 +1497,11 @@ static const nir_op op_trans[TGSI_OPCODE_LAST] = { [TGSI_OPCODE_UMIN] = nir_op_umin, [TGSI_OPCODE_UMOD] = nir_op_umod, [TGSI_OPCODE_UMUL] = nir_op_imul, - [TGSI_OPCODE_USEQ] = nir_op_ieq, - [TGSI_OPCODE_USGE] = nir_op_uge, + [TGSI_OPCODE_USEQ] = nir_op_ieq32, + [TGSI_OPCODE_USGE] = nir_op_uge32, [TGSI_OPCODE_USHR] = nir_op_ushr, - [TGSI_OPCODE_USLT] = nir_op_ult, - [TGSI_OPCODE_USNE] = nir_op_ine, + [TGSI_OPCODE_USLT] = nir_op_ult32, + [TGSI_OPCODE_USNE] = nir_op_ine32, [TGSI_OPCODE_SWITCH] = 0, /* not emitted by glsl_to_tgsi.cpp */ [TGSI_OPCODE_CASE] = 0, /* not emitted by glsl_to_tgsi.cpp */ diff --git a/src/gallium/drivers/vc4/vc4_program.c b/src/gallium/drivers/vc4/vc4_program.c index f8dce1b1dec..b85df172892 100644 --- a/src/gallium/drivers/vc4/vc4_program.c +++ b/src/gallium/drivers/vc4/vc4_program.c @@ -1004,24 +1004,24 @@ ntq_emit_comparison(struct vc4_compile *c, struct qreg *dest, enum qpu_cond cond; switch (compare_instr->op) { - case nir_op_feq: - case nir_op_ieq: + case nir_op_feq32: + case nir_op_ieq32: case nir_op_seq: cond = QPU_COND_ZS; break; - case nir_op_fne: - case nir_op_ine: + case nir_op_fne32: + case nir_op_ine32: case nir_op_sne: cond = QPU_COND_ZC; break; - case nir_op_fge: - case nir_op_ige: - case nir_op_uge: + case nir_op_fge32: + case nir_op_ige32: + case nir_op_uge32: case nir_op_sge: cond = QPU_COND_NC; break; - case nir_op_flt: - case nir_op_ilt: + case nir_op_flt32: + case nir_op_ilt32: case nir_op_slt: cond = QPU_COND_NS; break; @@ -1048,7 +1048,7 @@ ntq_emit_comparison(struct vc4_compile *c, struct qreg *dest, qir_uniform_f(c, 1.0), qir_uniform_f(c, 0.0)); break; - case nir_op_bcsel: + case nir_op_b32csel: *dest = qir_SEL(c, cond, ntq_get_alu_src(c, sel_instr, 1), ntq_get_alu_src(c, sel_instr, 2)); @@ -1264,21 +1264,21 @@ ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr) case nir_op_sne: case nir_op_sge: case nir_op_slt: - case nir_op_feq: - case nir_op_fne: - case nir_op_fge: - case nir_op_flt: - case nir_op_ieq: - case nir_op_ine: - case nir_op_ige: - case nir_op_uge: - case nir_op_ilt: + case nir_op_feq32: + case nir_op_fne32: + case nir_op_fge32: + case nir_op_flt32: + case nir_op_ieq32: + case nir_op_ine32: + case nir_op_ige32: + case nir_op_uge32: + case nir_op_ilt32: if (!ntq_emit_comparison(c, &result, instr, instr)) { fprintf(stderr, "Bad comparison instruction\n"); } break; - case nir_op_bcsel: + case nir_op_b32csel: result = ntq_emit_bcsel(c, instr, src); break; case nir_op_fcsel: diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 165c70c7c29..24d5e4bce98 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -1051,10 +1051,10 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) break; } - case nir_op_flt: - case nir_op_fge: - case nir_op_feq: - case nir_op_fne: { + case nir_op_flt32: + case nir_op_fge32: + case nir_op_feq32: + case nir_op_fne32: { fs_reg dest = result; const uint32_t bit_size = nir_src_bit_size(instr->src[0].src); @@ -1063,16 +1063,16 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) brw_conditional_mod cond; switch (instr->op) { - case nir_op_flt: + case nir_op_flt32: cond = BRW_CONDITIONAL_L; break; - case nir_op_fge: + case nir_op_fge32: cond = BRW_CONDITIONAL_GE; break; - case nir_op_feq: + case nir_op_feq32: cond = BRW_CONDITIONAL_Z; break; - case nir_op_fne: + case nir_op_fne32: cond = BRW_CONDITIONAL_NZ; break; default: @@ -1095,12 +1095,12 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) break; } - case nir_op_ilt: - case nir_op_ult: - case nir_op_ige: - case nir_op_uge: - case nir_op_ieq: - case nir_op_ine: { + case nir_op_ilt32: + case nir_op_ult32: + case nir_op_ige32: + case nir_op_uge32: + case nir_op_ieq32: + case nir_op_ine32: { fs_reg dest = result; const uint32_t bit_size = nir_src_bit_size(instr->src[0].src); @@ -1109,18 +1109,18 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) brw_conditional_mod cond; switch (instr->op) { - case nir_op_ilt: - case nir_op_ult: + case nir_op_ilt32: + case nir_op_ult32: cond = BRW_CONDITIONAL_L; break; - case nir_op_ige: - case nir_op_uge: + case nir_op_ige32: + case nir_op_uge32: cond = BRW_CONDITIONAL_GE; break; - case nir_op_ieq: + case nir_op_ieq32: cond = BRW_CONDITIONAL_Z; break; - case nir_op_ine: + case nir_op_ine32: cond = BRW_CONDITIONAL_NZ; break; default: @@ -1173,18 +1173,18 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) case nir_op_fdot2: case nir_op_fdot3: case nir_op_fdot4: - case nir_op_ball_fequal2: - case nir_op_ball_iequal2: - case nir_op_ball_fequal3: - case nir_op_ball_iequal3: - case nir_op_ball_fequal4: - case nir_op_ball_iequal4: - case nir_op_bany_fnequal2: - case nir_op_bany_inequal2: - case nir_op_bany_fnequal3: - case nir_op_bany_inequal3: - case nir_op_bany_fnequal4: - case nir_op_bany_inequal4: + case nir_op_b32all_fequal2: + case nir_op_b32all_iequal2: + case nir_op_b32all_fequal3: + case nir_op_b32all_iequal3: + case nir_op_b32all_fequal4: + case nir_op_b32all_iequal4: + case nir_op_b32any_fnequal2: + case nir_op_b32any_inequal2: + case nir_op_b32any_fnequal3: + case nir_op_b32any_inequal3: + case nir_op_b32any_fnequal4: + case nir_op_b32any_inequal4: unreachable("Lowered by nir_lower_alu_reductions"); case nir_op_fnoise1_1: @@ -1503,7 +1503,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) inst->saturate = instr->dest.saturate; break; - case nir_op_bcsel: + case nir_op_b32csel: if (optimize_frontfacing_ternary(instr, result)) return; diff --git a/src/intel/compiler/brw_nir_analyze_boolean_resolves.c b/src/intel/compiler/brw_nir_analyze_boolean_resolves.c index 4ad26e21103..b1be54d92ac 100644 --- a/src/intel/compiler/brw_nir_analyze_boolean_resolves.c +++ b/src/intel/compiler/brw_nir_analyze_boolean_resolves.c @@ -109,18 +109,18 @@ analyze_boolean_resolves_block(nir_block *block) uint8_t resolve_status; nir_alu_instr *alu = nir_instr_as_alu(instr); switch (alu->op) { - case nir_op_ball_fequal2: - case nir_op_ball_iequal2: - case nir_op_ball_fequal3: - case nir_op_ball_iequal3: - case nir_op_ball_fequal4: - case nir_op_ball_iequal4: - case nir_op_bany_fnequal2: - case nir_op_bany_inequal2: - case nir_op_bany_fnequal3: - case nir_op_bany_inequal3: - case nir_op_bany_fnequal4: - case nir_op_bany_inequal4: + case nir_op_b32all_fequal2: + case nir_op_b32all_iequal2: + case nir_op_b32all_fequal3: + case nir_op_b32all_iequal3: + case nir_op_b32all_fequal4: + case nir_op_b32all_iequal4: + case nir_op_b32any_fnequal2: + case nir_op_b32any_inequal2: + case nir_op_b32any_fnequal3: + case nir_op_b32any_inequal3: + case nir_op_b32any_fnequal4: + case nir_op_b32any_inequal4: /* These are only implemented by the vec4 backend and its * implementation emits resolved booleans. At some point in the * future, this may change and we'll have to remove some of the diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp index 4f97e96afa8..b6c926861fb 100644 --- a/src/intel/compiler/brw_vec4_nir.cpp +++ b/src/intel/compiler/brw_vec4_nir.cpp @@ -833,34 +833,34 @@ static enum brw_conditional_mod brw_conditional_for_nir_comparison(nir_op op) { switch (op) { - case nir_op_flt: - case nir_op_ilt: - case nir_op_ult: + case nir_op_flt32: + case nir_op_ilt32: + case nir_op_ult32: return BRW_CONDITIONAL_L; - case nir_op_fge: - case nir_op_ige: - case nir_op_uge: + case nir_op_fge32: + case nir_op_ige32: + case nir_op_uge32: return BRW_CONDITIONAL_GE; - case nir_op_feq: - case nir_op_ieq: - case nir_op_ball_fequal2: - case nir_op_ball_iequal2: - case nir_op_ball_fequal3: - case nir_op_ball_iequal3: - case nir_op_ball_fequal4: - case nir_op_ball_iequal4: + case nir_op_feq32: + case nir_op_ieq32: + case nir_op_b32all_fequal2: + case nir_op_b32all_iequal2: + case nir_op_b32all_fequal3: + case nir_op_b32all_iequal3: + case nir_op_b32all_fequal4: + case nir_op_b32all_iequal4: return BRW_CONDITIONAL_Z; - case nir_op_fne: - case nir_op_ine: - case nir_op_bany_fnequal2: - case nir_op_bany_inequal2: - case nir_op_bany_fnequal3: - case nir_op_bany_inequal3: - case nir_op_bany_fnequal4: - case nir_op_bany_inequal4: + case nir_op_fne32: + case nir_op_ine32: + case nir_op_b32any_fnequal2: + case nir_op_b32any_inequal2: + case nir_op_b32any_fnequal3: + case nir_op_b32any_inequal3: + case nir_op_b32any_fnequal4: + case nir_op_b32any_inequal4: return BRW_CONDITIONAL_NZ; default: @@ -880,20 +880,20 @@ vec4_visitor::optimize_predicate(nir_alu_instr *instr, nir_instr_as_alu(instr->src[0].src.ssa->parent_instr); switch (cmp_instr->op) { - case nir_op_bany_fnequal2: - case nir_op_bany_inequal2: - case nir_op_bany_fnequal3: - case nir_op_bany_inequal3: - case nir_op_bany_fnequal4: - case nir_op_bany_inequal4: + case nir_op_b32any_fnequal2: + case nir_op_b32any_inequal2: + case nir_op_b32any_fnequal3: + case nir_op_b32any_inequal3: + case nir_op_b32any_fnequal4: + case nir_op_b32any_inequal4: *predicate = BRW_PREDICATE_ALIGN16_ANY4H; break; - case nir_op_ball_fequal2: - case nir_op_ball_iequal2: - case nir_op_ball_fequal3: - case nir_op_ball_iequal3: - case nir_op_ball_fequal4: - case nir_op_ball_iequal4: + case nir_op_b32all_fequal2: + case nir_op_b32all_iequal2: + case nir_op_b32all_fequal3: + case nir_op_b32all_iequal3: + case nir_op_b32all_fequal4: + case nir_op_b32all_iequal4: *predicate = BRW_PREDICATE_ALIGN16_ALL4H; break; default: @@ -1334,18 +1334,18 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) case nir_op_fddy_fine: unreachable("derivatives are not valid in vertex shaders"); - case nir_op_ilt: - case nir_op_ult: - case nir_op_ige: - case nir_op_uge: - case nir_op_ieq: - case nir_op_ine: + case nir_op_ilt32: + case nir_op_ult32: + case nir_op_ige32: + case nir_op_uge32: + case nir_op_ieq32: + case nir_op_ine32: assert(nir_dest_bit_size(instr->dest.dest) < 64); /* Fallthrough */ - case nir_op_flt: - case nir_op_fge: - case nir_op_feq: - case nir_op_fne: { + case nir_op_flt32: + case nir_op_fge32: + case nir_op_feq32: + case nir_op_fne32: { enum brw_conditional_mod conditional_mod = brw_conditional_for_nir_comparison(instr->op); @@ -1366,14 +1366,14 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) break; } - case nir_op_ball_iequal2: - case nir_op_ball_iequal3: - case nir_op_ball_iequal4: + case nir_op_b32all_iequal2: + case nir_op_b32all_iequal3: + case nir_op_b32all_iequal4: assert(nir_dest_bit_size(instr->dest.dest) < 64); /* Fallthrough */ - case nir_op_ball_fequal2: - case nir_op_ball_fequal3: - case nir_op_ball_fequal4: { + case nir_op_b32all_fequal2: + case nir_op_b32all_fequal3: + case nir_op_b32all_fequal4: { unsigned swiz = brw_swizzle_for_size(nir_op_infos[instr->op].input_sizes[0]); @@ -1385,14 +1385,14 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) break; } - case nir_op_bany_inequal2: - case nir_op_bany_inequal3: - case nir_op_bany_inequal4: + case nir_op_b32any_inequal2: + case nir_op_b32any_inequal3: + case nir_op_b32any_inequal4: assert(nir_dest_bit_size(instr->dest.dest) < 64); /* Fallthrough */ - case nir_op_bany_fnequal2: - case nir_op_bany_fnequal3: - case nir_op_bany_fnequal4: { + case nir_op_b32any_fnequal2: + case nir_op_b32any_fnequal3: + case nir_op_b32any_fnequal4: { unsigned swiz = brw_swizzle_for_size(nir_op_infos[instr->op].input_sizes[0]); @@ -1792,7 +1792,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) inst->saturate = instr->dest.saturate; break; - case nir_op_bcsel: + case nir_op_b32csel: enum brw_predicate predicate; if (!optimize_predicate(instr, &predicate)) { emit(CMP(dst_null_d(), op[0], brw_imm_d(0), BRW_CONDITIONAL_NZ)); -- 2.19.2 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev