Seems reasonable though I thought you had patches to the constant combining
to fix this. Maybe they'll be ready in time that we won't need this?
On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga <ito...@igalia.com> wrote:
> 3-src instructions don't support immediates, but since 36bc5f06dd22,
> we allow them on MAD and LRP relying on the combine constants pass to
> fix it up later. However, that pass is specialized for 32-bit float
> immediates and can't handle HF constants at present, so this patch
> ensures that copy-propagation only does this for 32-bit constants.
> ---
> src/intel/compiler/brw_fs_copy_propagation.cpp | 12 ++++++++++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/src/intel/compiler/brw_fs_copy_propagation.cpp
> b/src/intel/compiler/brw_fs_copy_propagation.cpp
> index ab34b63748e..58d5080b4e9 100644
> --- a/src/intel/compiler/brw_fs_copy_propagation.cpp
> +++ b/src/intel/compiler/brw_fs_copy_propagation.cpp
> @@ -741,8 +741,16 @@ fs_visitor::try_constant_propagate(fs_inst *inst,
> acp_entry *entry)
>
> case BRW_OPCODE_MAD:
> case BRW_OPCODE_LRP:
> - inst->src[i] = val;
> - progress = true;
> + /* 3-src instructions can't take IMM registers, however, for
> 32-bit
> + * floating instructions we rely on the combine constants pass
> to fix
> + * it up. For anything else, we shouldn't be promoting immediates
> + * until we can make the pass capable of combining constants of
> + * different sizes.
> + */
> + if (val.type == BRW_REGISTER_TYPE_F) {
> + inst->src[i] = val;
> + progress = true;
> + }
> break;
>
> default:
> --
> 2.17.1
>
> _______________________________________________
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
