Gen9-10 have fewer than 4 subslices per slice, so they need this to be
rounded up. Gen11 isn't documented as needing this hack, and it can
also have more than 4 subslices, so the hack actually can break things.
---
src/mesa/drivers/dri/i965/brw_program.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
I have not tested this patch. I made the equivalent change to iris and
it fixed some geometry shader tests that were spilling (but don't spill
on i965 - that's a compiler quality regression I have yet to fix)
diff --git a/src/mesa/drivers/dri/i965/brw_program.c
b/src/mesa/drivers/dri/i965/brw_program.c
index 96247f32f0f..730d6dc0d5a 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -407,7 +407,7 @@ brw_alloc_stage_scratch(struct brw_context *brw,
* and we wish to view that there are 4 subslices per slice
* instead of the actual number of subslices per slice.
*/
- if (devinfo->gen >= 9)
+ if (devinfo->gen >= 9 && devinfo->gen < 11)
subslices = 4 * brw->screen->devinfo.num_slices;
unsigned scratch_ids_per_subslice;
--
2.19.1
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