v3: rebase v3: move RA code into it's own function Signed-off-by: Rhys Perry <pendingchao...@gmail.com> --- src/gallium/drivers/nouveau/codegen/nv50_ir.h | 4 +++ .../nouveau/codegen/nv50_ir_emit_gm107.cpp | 34 ++++++++++++------- .../drivers/nouveau/codegen/nv50_ir_print.cpp | 17 ++++++++++ .../drivers/nouveau/codegen/nv50_ir_ra.cpp | 31 +++++++++++++++++ 4 files changed, 74 insertions(+), 12 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.h b/src/gallium/drivers/nouveau/codegen/nv50_ir.h index 8085bb2f54..2388f3923c 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir.h +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir.h @@ -224,6 +224,10 @@ enum operation #define NV50_IR_SUBOP_SULD_ZERO 0 #define NV50_IR_SUBOP_SULD_TRAP 1 #define NV50_IR_SUBOP_SULD_SDCL 3 +// These three are only for GM107+ and are set during register allocation +#define NV50_IR_SUBOP_SULDP_RGBA (0 << 2) +#define NV50_IR_SUBOP_SULDP_RG (1 << 2) +#define NV50_IR_SUBOP_SULDP_R (2 << 2) #define NV50_IR_SUBOP_SUBFM_3D 1 #define NV50_IR_SUBOP_SUCLAMP_2D 0x10 #define NV50_IR_SUBOP_SUCLAMP_SD(r, d) (( 0 + (r)) | ((d == 2) ? 0x10 : 0)) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp index be00db3131..d7f4380b34 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp @@ -3257,26 +3257,36 @@ void CodeEmitterGM107::emitSULDx() { const TexInstruction *insn = this->insn->asTex(); - int type = 0; emitInsn(0xeb000000); if (insn->op == OP_SULDB) emitField(0x34, 1, 1); emitSUTarget(); - switch (insn->dType) { - case TYPE_S8: type = 1; break; - case TYPE_U16: type = 2; break; - case TYPE_S16: type = 3; break; - case TYPE_U32: type = 4; break; - case TYPE_U64: type = 5; break; - case TYPE_B128: type = 6; break; - default: - assert(insn->dType == TYPE_U8); - break; + if (insn->op == OP_SULDB) { + int type = 0; + switch (insn->dType) { + case TYPE_S8: type = 1; break; + case TYPE_U16: type = 2; break; + case TYPE_S16: type = 3; break; + case TYPE_U32: type = 4; break; + case TYPE_U64: type = 5; break; + case TYPE_B128: type = 6; break; + default: + assert(insn->dType == TYPE_U8); + break; + } + emitField(0x14, 3, type); + } else { + int type = 0; + switch (insn->subOp & 0xc) { + case NV50_IR_SUBOP_SULDP_R: type = 0x1; break; + case NV50_IR_SUBOP_SULDP_RG: type = 0x3; break; + case NV50_IR_SUBOP_SULDP_RGBA: type = 0xf; break; + } + emitField(0x14, 4, type); } emitLDSTc(0x18); - emitField(0x14, 3, type); emitGPR (0x00, insn->def(0)); emitGPR (0x08, insn->src(0)); diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp index 5dcbf3c3e0..43011c23af 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp @@ -246,6 +246,16 @@ static const char *xmadOpCModeStr[] = "clo", "chi", "csfu", "cbcc" }; +static const char *suldOpStr[] = +{ + "zero", "trap", "sdcl" +}; + +static const char *suldSwizzleOpStr[] = +{ + "rgba", "rg", "r" +}; + static const char *DataTypeStr[] = { "-", @@ -672,6 +682,13 @@ void Instruction::print() const PRINT("h%d ", (subOp & NV50_IR_SUBOP_XMAD_H1(i)) ? 1 : 0); break; } + case OP_SULDB: + case OP_SULDP: + if ((subOp & 0x3) < ARRAY_SIZE(suldOpStr)) + PRINT("%s ", suldOpStr[subOp & 0x3]); + if (op == OP_SULDP && subOp >> 2 < (int)ARRAY_SIZE(suldSwizzleOpStr)) + PRINT("%s ", suldSwizzleOpStr[subOp >> 2]); + break; default: if (subOp) PRINT("(SUBOP:%u) ", subOp); diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp index 322b79fe62..8e57bda254 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp @@ -264,6 +264,7 @@ private: void addHazard(Instruction *i, const ValueRef *src); void textureMask(TexInstruction *); + void suldpMask(TexInstruction *); void addConstraint(Instruction *, int s, int n); bool detectConflict(Instruction *, int s); @@ -1996,6 +1997,33 @@ RegAlloc::InsertConstraintsPass::textureMask(TexInstruction *tex) tex->setDef(c, NULL); } +void +RegAlloc::InsertConstraintsPass::suldpMask(TexInstruction *tex) +{ + int max = 0; + for (int d = 0; tex->defExists(d); d++) { + if (tex->getDef(d)->refCount()) + max = d; + } + + switch (max) { + case 0: + tex->subOp |= NV50_IR_SUBOP_SULDP_R; + tex->setDef(1, NULL); + tex->setDef(2, NULL); + tex->setDef(3, NULL); + break; + case 1: + tex->subOp |= NV50_IR_SUBOP_SULDP_RG; + tex->setDef(2, NULL); + tex->setDef(3, NULL); + break; + default: + tex->subOp |= NV50_IR_SUBOP_SULDP_RGBA; + break; + } +} + bool RegAlloc::InsertConstraintsPass::detectConflict(Instruction *cst, int s) { @@ -2297,6 +2325,9 @@ RegAlloc::InsertConstraintsPass::texConstraintGM107(TexInstruction *tex) if (isTextureOp(tex->op)) textureMask(tex); + else + if (tex->op == OP_SULDP) + suldpMask(tex); if (isScalarTexGM107(tex)) { handleScalarTexGM107(tex); -- 2.20.1 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev