On Tue, Jan 22, 2019 at 11:53 AM Francisco Jerez <curroje...@riseup.net> wrote: > > Matt Turner <matts...@gmail.com> writes: > > > emit_uniformize() emits SHADER_OPCODE_FIND_LIVE_CHANNEL with its > > flag_subreg set, so that the IR knows which flag is accessed. However > > the flag is only used on Gen7 in Align1 mode, and it is used as an > > explicit source and destination. > > > > To avoid setting unnecessary bits in the instruction words, get the > > information we need and reset the default flag register. This allows > > round-tripping through the assembler/disassembler. > > --- > > src/intel/compiler/brw_eu_emit.c | 11 ++++++++--- > > 1 file changed, 8 insertions(+), 3 deletions(-) > > > > diff --git a/src/intel/compiler/brw_eu_emit.c > > b/src/intel/compiler/brw_eu_emit.c > > index 45e2552783b..e6f6d6419d2 100644 > > --- a/src/intel/compiler/brw_eu_emit.c > > +++ b/src/intel/compiler/brw_eu_emit.c > > @@ -3312,6 +3312,14 @@ brw_find_live_channel(struct brw_codegen *p, struct > > brw_reg dst, > > > > brw_push_insn_state(p); > > > > + /* The flag register is only used on Gen7 in align1 mode, so avoid > > setting > > + * unnecessary bits in the instruction words, get the information we > > need > > + * and reset the default flag register. > > + */ > > + const struct brw_reg flag = brw_flag_reg(p->current->flag_subreg / 2, > > + p->current->flag_subreg % 2); > > + brw_set_default_flag_reg(p, 0, 0); > > + > > I think this is going to break Gen7, because the MOV instructions > emitted in the loop below have conditional mod enabled and won't be > pointing at the right flag register anymore after this change.
Crap, I missed that. I'll send an updated patch. _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev