From: Nicolai Hähnle <[email protected]>
This field was added in a recent addrlib update, and while there
currently seems to be no issue with skipping it, we will have to
set it correctly in the future.
---
src/amd/common/ac_surface.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 91004e032a3..27e63c318e6 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -1135,20 +1135,21 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
hin.hTileFlags.pipeAligned = !in->flags.metaPipeUnaligned;
hin.hTileFlags.rbAligned = !in->flags.metaRbUnaligned;
hin.depthFlags = in->flags;
hin.swizzleMode = in->swizzleMode;
hin.unalignedWidth = in->width;
hin.unalignedHeight = in->height;
hin.numSlices = in->numSlices;
hin.numMipLevels = in->numMipLevels;
+ hin.firstMipIdInTail = out.firstMipIdInTail;
ret = Addr2ComputeHtileInfo(addrlib, &hin, &hout);
if (ret != ADDR_OK)
return ret;
surf->u.gfx9.htile.rb_aligned = hin.hTileFlags.rbAligned;
surf->u.gfx9.htile.pipe_aligned = hin.hTileFlags.pipeAligned;
surf->htile_size = hout.htileBytes;
surf->htile_slice_size = hout.sliceSize;
surf->htile_alignment = hout.baseAlign;
@@ -1201,20 +1202,21 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
din.colorFlags = in->flags;
din.resourceType = in->resourceType;
din.swizzleMode = in->swizzleMode;
din.bpp = in->bpp;
din.unalignedWidth = in->width;
din.unalignedHeight = in->height;
din.numSlices = in->numSlices;
din.numFrags = in->numFrags;
din.numMipLevels = in->numMipLevels;
din.dataSurfaceSize = out.surfSize;
+ din.firstMipIdInTail = out.firstMipIdInTail;
ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
if (ret != ADDR_OK)
return ret;
surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
surf->u.gfx9.dcc.pipe_aligned =
din.dccKeyFlags.pipeAligned;
surf->u.gfx9.dcc_pitch_max = dout.pitch - 1;
surf->dcc_size = dout.dccRamSize;
surf->dcc_alignment = dout.dccRamBaseAlign;
--
2.19.1
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