This series introduces a new ir3-specific NIR pass that moves offset computations for different IO ops that currently occur in the backend, to NIR.
For now, it handles image store/atomics, and SSBO load/store/atomics. Lowering UBO offsets is WIP and will probably be sent as follow up patches. The lowering for image ops doesn't seem to help much in shader instruction stats, but it does simplify backend code. The lowering for SSBO however helps significantly. It saves potentially one or more instructions for each SSBO load, store or atomic access in a shader. Quite a few freedreno specific intrinsics are added, which is not new (intel has some) but uncommon. I guess we will have to live with it while NIR doesn't offer all the flexibility needed by backends. A git tree of this series can be checked out at: https://gitlab.freedesktop.org/elima/mesa/tree/fd/lower-io-offsets We have only tested it on a5xx. Eduardo Lima Mitev (9): nir: Add a new intrinsic 'image_deref_load_param_ir3' ir3/compiler: Handle newly added intrinsic image_deref_load_param_ir3 nir: Add a new ALU nir_op_imad24_ir3 ir3_compiler/nir: Handle newly added opcode nir_op_imad24_ir3 ir3/nir: Add a new pass 'ir3_nir_lower_io_offsets' ir3/compiler: Use the new lower_io_offsets pass nir: Add ir3-specific version of most SSBO intrinsics ir3: Extend lower_io_offsets pass to lower SSBO dword offset computation ir3/compiler: Handle the new ir3 intrinsics for SSBO src/compiler/nir/nir_intrinsics.py | 43 ++ src/compiler/nir/nir_opcodes.py | 16 + src/freedreno/Makefile.sources | 1 + src/freedreno/ir3/ir3_compiler_nir.c | 133 ++--- src/freedreno/ir3/ir3_nir.c | 1 + src/freedreno/ir3/ir3_nir.h | 1 + src/freedreno/ir3/ir3_nir_lower_io_offsets.c | 492 +++++++++++++++++++ 7 files changed, 631 insertions(+), 56 deletions(-) create mode 100644 src/freedreno/ir3/ir3_nir_lower_io_offsets.c -- 2.20.1 _______________________________________________ mesa-dev mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-dev
