From: Marek Olšák <marek.ol...@amd.com>

---
 .../radeonsi/si_compute_prim_discard.c        | 20 ++++++++++---------
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_compute_prim_discard.c 
b/src/gallium/drivers/radeonsi/si_compute_prim_discard.c
index 1b36bd6ca53..afb7424aa41 100644
--- a/src/gallium/drivers/radeonsi/si_compute_prim_discard.c
+++ b/src/gallium/drivers/radeonsi/si_compute_prim_discard.c
@@ -1079,41 +1079,43 @@ si_prepare_prim_discard_or_split_draw(struct si_context 
*sctx,
        struct radeon_cmdbuf *cs = sctx->prim_discard_compute_cs;
        bool compute_has_space = sctx->ws->cs_check_space(cs, need_compute_dw);
        assert(compute_has_space);
        assert(si_check_ring_space(sctx, out_indexbuf_size));
        return SI_PRIM_DISCARD_ENABLED;
 }
 
 void si_compute_signal_gfx(struct si_context *sctx)
 {
        struct radeon_cmdbuf *cs = sctx->prim_discard_compute_cs;
-       bool inv_L2 = sctx->chip_class <= CIK && VERTEX_COUNTER_GDS_MODE == 0;
-       bool writeback_L2 = sctx->chip_class == VI && VERTEX_COUNTER_GDS_MODE 
== 0;
+       unsigned writeback_L2_flags = 0;
+
+       /* The writeback L2 flags vary with each chip generation. */
+       /* CI needs to flush vertex indices to memory. */
+       if (sctx->chip_class <= CIK)
+               writeback_L2_flags = EVENT_TC_WB_ACTION_ENA;
+       else if (sctx->chip_class == VI && VERTEX_COUNTER_GDS_MODE == 0)
+               writeback_L2_flags = EVENT_TC_WB_ACTION_ENA | 
EVENT_TC_NC_ACTION_ENA;
 
        if (!sctx->compute_num_prims_in_batch)
                return;
 
        assert(sctx->compute_rewind_va);
 
        /* After the queued dispatches are done and vertex counts are written to
         * the gfx IB, signal the gfx IB to continue. CP doesn't wait for
         * the dispatches to finish, it only adds the CS_DONE event into the 
event
         * queue.
-        *
-        * Need to writeback the vertex count on VI, so that CP can see it.
         */
-       si_cp_release_mem(sctx, cs, V_028A90_CS_DONE,
-                         inv_L2 ? EVENT_TC_ACTION_ENA :
-                         writeback_L2 ? EVENT_TC_WB_ACTION_ENA | 
EVENT_TC_NC_ACTION_ENA : 0,
+       si_cp_release_mem(sctx, cs, V_028A90_CS_DONE, writeback_L2_flags,
                          sctx->chip_class <= VI ? EOP_DST_SEL_MEM : 
EOP_DST_SEL_TC_L2,
-                         inv_L2 || writeback_L2 ? 
EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM :
-                                                  EOP_INT_SEL_NONE,
+                         writeback_L2_flags ? 
EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM :
+                                              EOP_INT_SEL_NONE,
                          EOP_DATA_SEL_VALUE_32BIT,
                          NULL,
                          sctx->compute_rewind_va |
                          ((uint64_t)sctx->screen->info.address32_hi << 32),
                          REWIND_SIGNAL_BIT, /* signaling value for the REWIND 
packet */
                          SI_NOT_QUERY);
 
        sctx->compute_rewind_va = 0;
        sctx->compute_num_prims_in_batch = 0;
 }
-- 
2.17.1

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