Honestly the zero tests is worrying me. This is a pretty big extension
and I have questions like:
to 16-bit loads + 16-bit ALU actually work together or have we been
silently relying on the fact there is always a ZExt cast after and
that did not care about input size?
On Thu, Mar 21, 2019 at 10:03 AM Samuel Pitoiset
<samuel.pitoi...@gmail.com> wrote:
>
> Should be safe to enable as all instructions seem to support 16-bit.
> Unfortunately, there is no CTS test.
>
> Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
> ---
> src/amd/vulkan/radv_extensions.py | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/src/amd/vulkan/radv_extensions.py
> b/src/amd/vulkan/radv_extensions.py
> index 421f8b926ea..23106765c2a 100644
> --- a/src/amd/vulkan/radv_extensions.py
> +++ b/src/amd/vulkan/radv_extensions.py
> @@ -122,6 +122,7 @@ EXTENSIONS = [
> Extension('VK_EXT_vertex_attribute_divisor', 3, True),
> Extension('VK_AMD_draw_indirect_count', 1, True),
> Extension('VK_AMD_gcn_shader', 1, True),
> + Extension('VK_AMD_gpu_shader_half_float', 1,
> 'device->rad_info.chip_class >= VI && HAVE_LLVM >= 0x0800'),
> Extension('VK_AMD_rasterization_order', 1,
> 'device->has_out_of_order_rast'),
> Extension('VK_AMD_shader_core_properties', 1, True),
> Extension('VK_AMD_shader_info', 1, True),
> --
> 2.21.0
>
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