On Wed, Mar 27, 2019 at 9:47 AM Topi Pohjolainen
<topi.pohjolai...@gmail.com> wrote:
>
> Similarly to 1cc17fb731466c68586915acbb916586457b19bc
>
> Fixes gpu hangs with dEQP-VK.tessellation.shader_input_output.barrier
>
> CC: Anuj Phogat <anuj.pho...@gmail.com>
> CC: Clayton Craft <clayton.a.cr...@intel.com>
> Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
> ---
> src/intel/compiler/brw_fs_nir.cpp | 21 +++++++++++++++------
> 1 file changed, 15 insertions(+), 6 deletions(-)
>
> diff --git a/src/intel/compiler/brw_fs_nir.cpp
> b/src/intel/compiler/brw_fs_nir.cpp
> index 747529e72d8..ee8274de65a 100644
> --- a/src/intel/compiler/brw_fs_nir.cpp
> +++ b/src/intel/compiler/brw_fs_nir.cpp
> @@ -2458,15 +2458,24 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
> &bld,
> bld.exec_all().MOV(m0, brw_imm_ud(0u));
>
> /* Copy "Barrier ID" from r0.2, bits 16:13 */
> - chanbld.AND(m0_2, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD),
> - brw_imm_ud(INTEL_MASK(16, 13)));
> + if (devinfo->gen < 11) {
> + chanbld.AND(m0_2, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD),
> + brw_imm_ud(INTEL_MASK(16, 13)));
>
> - /* Shift it up to bits 27:24. */
> - chanbld.SHL(m0_2, m0_2, brw_imm_ud(11));
> + /* Shift it up to bits 27:24. */
> + chanbld.SHL(m0_2, m0_2, brw_imm_ud(11));
> + } else {
> + chanbld.AND(m0_2, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD),
> + brw_imm_ud(INTEL_MASK(30, 24)));
> + }
>
> /* Set the Barrier Count and the enable bit */
> - chanbld.OR(m0_2, m0_2,
> - brw_imm_ud(tcs_prog_data->instances << 9 | (1 << 15)));
> + if (devinfo->gen < 11)
> + chanbld.OR(m0_2, m0_2,
> + brw_imm_ud(tcs_prog_data->instances << 9 | (1 << 15)));
> + else
> + chanbld.OR(m0_2, m0_2,
> + brw_imm_ud(tcs_prog_data->instances << 8 | (1 << 15)));
>
> bld.emit(SHADER_OPCODE_BARRIER, bld.null_reg_ud(), m0);
> break;
> --
> 2.13.6
>
Fixes the gpu hang.
Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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