In the FS IR we pretend that the instruction is predicated with (+f0.1)
just for flag dependency tracking purposes. Since the instruction
doesn't support predication before Haswell, we unset the predicate so we
should also unset the flag register so that we can round-trip the
disassembly.
---
src/intel/compiler/brw_fs_generator.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/compiler/brw_fs_generator.cpp
b/src/intel/compiler/brw_fs_generator.cpp
index af8350aed6c..84909f83fec 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -363,6 +363,7 @@ fs_generator::generate_fb_write(fs_inst *inst, struct
brw_reg payload)
{
if (devinfo->gen < 8 && !devinfo->is_haswell) {
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
+ brw_set_default_flag_reg(p, 0, 0);
}
const struct brw_reg implied_header =
--
2.21.0
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