From: Nicolai Hähnle <nicolai.haeh...@amd.com>
These functions are now only used in LS/HS shaders (both separate and
merged).
---
src/gallium/drivers/radeonsi/si_shader.c | 33 ++++++++++++------------
1 file changed, 16 insertions(+), 17 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index f95a96f2458..d127b525963 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -999,68 +999,68 @@ static LLVMValueRef buffer_load(struct
lp_build_tgsi_context *bld_base,
value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
swizzle * 4, 1, 0, can_speculate, false);
value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
swizzle * 4 + 4, 1, 0, can_speculate, false);
return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
}
/**
- * Load from LDS.
+ * Load from LSHS LDS storage.
*
* \param type output value type
* \param swizzle offset (typically 0..3); it can be ~0, which loads a
vec4
* \param dw_addr address in dwords
*/
-static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
+static LLVMValueRef lshs_lds_load(struct lp_build_tgsi_context *bld_base,
LLVMTypeRef type, unsigned swizzle,
LLVMValueRef dw_addr)
{
struct si_shader_context *ctx = si_shader_context(bld_base);
LLVMValueRef value;
if (swizzle == ~0) {
LLVMValueRef values[TGSI_NUM_CHANNELS];
for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
- values[chan] = lds_load(bld_base, type, chan, dw_addr);
+ values[chan] = lshs_lds_load(bld_base, type, chan,
dw_addr);
return ac_build_gather_values(&ctx->ac, values,
TGSI_NUM_CHANNELS);
}
/* Split 64-bit loads. */
if (llvm_type_is_64bit(ctx, type)) {
LLVMValueRef lo, hi;
- lo = lds_load(bld_base, ctx->i32, swizzle, dw_addr);
- hi = lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
+ lo = lshs_lds_load(bld_base, ctx->i32, swizzle, dw_addr);
+ hi = lshs_lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
}
dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
LLVMConstInt(ctx->i32, swizzle, 0), "");
value = ac_lds_load(&ctx->ac, dw_addr);
return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
}
/**
- * Store to LDS.
+ * Store to LSHS LDS storage.
*
* \param swizzle offset (typically 0..3)
* \param dw_addr address in dwords
* \param value value to store
*/
-static void lds_store(struct si_shader_context *ctx,
+static void lshs_lds_store(struct si_shader_context *ctx,
unsigned dw_offset_imm, LLVMValueRef dw_addr,
LLVMValueRef value)
{
dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
LLVMConstInt(ctx->i32, dw_offset_imm, 0), "");
ac_lds_store(&ctx->ac, dw_addr, value);
}
enum si_tess_ring {
@@ -1110,21 +1110,21 @@ static LLVMValueRef fetch_input_tcs(
const struct tgsi_full_src_register *reg,
enum tgsi_opcode_type type, unsigned swizzle_in)
{
struct si_shader_context *ctx = si_shader_context(bld_base);
LLVMValueRef dw_addr, stride;
unsigned swizzle = swizzle_in & 0xffff;
stride = get_tcs_in_vertex_dw_stride(ctx);
dw_addr = get_tcs_in_current_patch_offset(ctx);
dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
- return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
dw_addr);
+ return lshs_lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
dw_addr);
}
static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi,
LLVMTypeRef type,
LLVMValueRef vertex_index,
LLVMValueRef param_index,
unsigned const_index,
unsigned location,
unsigned driver_location,
unsigned component,
@@ -1177,21 +1177,21 @@ static LLVMValueRef si_nir_load_tcs_varyings(struct
ac_shader_abi *abi,
names, indices,
is_patch);
LLVMValueRef value[4];
for (unsigned i = 0; i < num_components; i++) {
unsigned offset = i;
if (llvm_type_is_64bit(ctx, type))
offset *= 2;
offset += component;
- value[i + component] = lds_load(bld_base, type, offset,
dw_addr);
+ value[i + component] = lshs_lds_load(bld_base, type, offset,
dw_addr);
}
return ac_build_varying_gather_values(&ctx->ac, value, num_components,
component);
}
static LLVMValueRef fetch_output_tcs(
struct lp_build_tgsi_context *bld_base,
const struct tgsi_full_src_register *reg,
enum tgsi_opcode_type type, unsigned swizzle_in)
{
@@ -1201,21 +1201,21 @@ static LLVMValueRef fetch_output_tcs(
if (reg->Register.Dimension) {
stride = get_tcs_out_vertex_dw_stride(ctx);
dw_addr = get_tcs_out_current_patch_offset(ctx);
dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
} else {
dw_addr = get_tcs_out_current_patch_data_offset(ctx);
dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
}
- return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
dw_addr);
+ return lshs_lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
dw_addr);
}
static LLVMValueRef fetch_input_tes(
struct lp_build_tgsi_context *bld_base,
const struct tgsi_full_src_register *reg,
enum tgsi_opcode_type type, unsigned swizzle_in)
{
struct si_shader_context *ctx = si_shader_context(bld_base);
LLVMValueRef base, addr;
unsigned swizzle = (swizzle_in & 0xffff);
@@ -1339,21 +1339,21 @@ static void store_output_tcs(struct
lp_build_tgsi_context *bld_base,
uint32_t writemask = reg->Register.WriteMask;
while (writemask) {
chan_index = u_bit_scan(&writemask);
LLVMValueRef value = dst[chan_index];
if (inst->Instruction.Saturate)
value = ac_build_clamp(&ctx->ac, value);
/* Skip LDS stores if there is no LDS read of this output. */
if (!skip_lds_store)
- lds_store(ctx, chan_index, dw_addr, value);
+ lshs_lds_store(ctx, chan_index, dw_addr, value);
value = ac_to_integer(&ctx->ac, value);
values[chan_index] = value;
if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
buf_addr, base,
4 * chan_index, 1, 0, true,
false);
}
@@ -1455,21 +1455,21 @@ static void si_nir_store_output_tcs(struct
ac_shader_abi *abi,
info->output_semantic_index,
is_patch);
for (unsigned chan = 0; chan < 4; chan++) {
if (!(writemask & (1 << chan)))
continue;
LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan -
component);
/* Skip LDS stores if there is no LDS read of this output. */
if (!skip_lds_store)
- lds_store(ctx, chan, dw_addr, value);
+ lshs_lds_store(ctx, chan, dw_addr, value);
value = ac_to_integer(&ctx->ac, value);
values[chan] = value;
if (writemask != 0xF && !is_tess_factor) {
ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
addr, base,
4 * chan, 1, 0, true,
false);
}
@@ -2964,22 +2964,21 @@ static void si_copy_tcs_inputs(struct
lp_build_tgsi_context *bld_base)
LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
LLVMConstInt(ctx->i32, 4 * i, 0),
"");
LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
get_rel_patch_id(ctx),
invocation_id,
LLVMConstInt(ctx->i32, i, 0));
- LLVMValueRef value = lds_load(bld_base, ctx->ac.i32, ~0,
- lds_ptr);
+ LLVMValueRef value = lshs_lds_load(bld_base, ctx->ac.i32, ~0,
lds_ptr);
ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4,
buffer_addr,
buffer_offset, 0, 1, 0, true,
false);
}
}
static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
LLVMValueRef rel_patch_id,
LLVMValueRef invocation_id,
LLVMValueRef
tcs_out_current_patch_data_offset,
@@ -3051,25 +3050,25 @@ static void si_write_tess_factors(struct
lp_build_tgsi_context *bld_base,
lds_base = tcs_out_current_patch_data_offset;
lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
LLVMConstInt(ctx->i32,
tess_inner_index * 4, 0),
"");
lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
LLVMConstInt(ctx->i32,
tess_outer_index * 4, 0),
"");
for (i = 0; i < outer_comps; i++) {
outer[i] = out[i] =
- lds_load(bld_base, ctx->ac.i32, i, lds_outer);
+ lshs_lds_load(bld_base, ctx->ac.i32, i,
lds_outer);
}
for (i = 0; i < inner_comps; i++) {
inner[i] = out[outer_comps+i] =
- lds_load(bld_base, ctx->ac.i32, i, lds_inner);
+ lshs_lds_load(bld_base, ctx->ac.i32, i,
lds_inner);
}
}
if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
/* For isolines, the hardware expects tess factors in the
* reverse order from what GLSL / TGSI specify.
*/
LLVMValueRef tmp = out[0];
out[0] = out[1];
out[1] = tmp;
@@ -3385,21 +3384,21 @@ static void si_llvm_emit_ls_epilogue(struct
ac_shader_abi *abi,
continue;
int param = si_shader_io_get_unique_index(name, index, false);
LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder,
base_dw_addr,
LLVMConstInt(ctx->i32, param * 4, 0),
"");
for (chan = 0; chan < 4; chan++) {
if (!(info->output_usagemask[i] & (1 << chan)))
continue;
- lds_store(ctx, chan, dw_addr,
+ lshs_lds_store(ctx, chan, dw_addr,
LLVMBuildLoad(ctx->ac.builder, addrs[4 * i +
chan], ""));
}
}
if (ctx->screen->info.chip_class >= GFX9)
si_set_ls_return_value_for_tcs(ctx);
}
static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
unsigned max_outputs,
--
2.20.1
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